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1 hd66730/hd66731 (dot-matrix liquid crystal display controller/driver supporting japanese kanji, korean font display) description the hd66730/1 is a dot-matrix liquid crystal display controller (lcd) and driver lsi that displays japanese characters consisting of kanji, hiragana and katakana according to the japanese industrial standard (jis) level-1 kanji set. the hd66730/1 incorporates the following five functions on a single chip: (i) display control function for the dot matrix lcd, (ii) a display ram to store character codes, (iii) rom fonts to support kanji, (iv) liquid crystal driver, and (v) a booster to drive the lcd. a two 6-character (hd66730) or four 10-character (hd66731) kanji display can easily be achieved by receiving character codes (2 bytes/character) from the mpu. the font rom includes 2,965 kanji from the jis level-1 kanji set, 524 jis non-kanji characters, and 128 half-size alphanumeric characters and symbols. full-size fonts such as japanese kanji and half-size of fonts such as alphanumeric characters can be displayed together. in addition, display control equivalent to full bit mapping can be performed through horizontal and vertical dot-by-dot smooth scroll functions for each display line. to help make systems more compact, a three-line clock synchronous serial transfer method is adopted in addition to an 8-bit bus for interfacing with a microcomputer. features dot-matrix liquid crystal display controller/driver supporting the display of kanji according to jis level-1 kanji set large character generator rom: 510 kbits ? kanji according to jis level-1 kanji set (11 12 dots): 2,965-character font ? jis non-kanji (11 12 dots): 524-character font ? half-size alphanumeric characters and symbols (5 12 dots): 128-character font display of 11 12 dots for full-size fonts consisting of kanji and kana, 5 12 dots for half-size fonts of alphanumeric characters and symbols in the same display 2-line 6-character full-size font display with a single chip (hd66730) 4-line 10-character full-size font display with a single chip (hd66731) expansion driver interface: maximum 2-line 20-character (or 4-line 10-character) display (hd66730) dot matrix font and 71 marks and icons (96 at hd66731)
hd66730/hd66731 2 various display control functions: horizontal smooth scroll (in dot units), vertical smooth scroll, white black inversion/blinking/white black inversion blinking character display, cursor display, display on/off display data ram: 40 2 bytes (stores codes to support 40 characters in a full-size font) character generator ram: 8 26 bytes (displays 8 characters of a 12 13 dot user font) 16-byte 96-segment ram three-line clock synchronous serial bus, 8-bit bus interface built-in double/triple liquid-crystal voltage booster circuit and built-in oscillator (operating frequency can be adjusted through external resistors) operating power supply voltage: 2.4v to 5.5v; liquid crystal display voltage: 3.0v to 13.0v hd66730: qfp 1420-128 (0.5 mm pitch), bare-chip hd66731: tcp-171 (straight), tcp-206 (bent), chip with bump list 1 programmable duty cycles duty drive number of display characters in full-size font number of segments/marks setting hd66730 hd66731 hd66730 hd66731 1/14 one 6-character one 10-character 71pcs 96pcs 1/27 two 6-character two 10-character 71pcs 96pcs 1/40 three 10-characters 96pcs 1/53 four 10-characters 96pcs ordering information type no. package number of display character cgrom hd66730a00fs fp-128 two 6-characters jis level-1 kanji (a00) hcd66730a00 bare chip two 6-characters hd66731a00ta0l straight tcp three 8-characters hd66731a00tb0l bending tcp four 10-characters hcd66731a00bp au-bumped chip four 10-characters hd66730a01fs fp-128 two 6-characters korean font (a01) hcd66730a01 bare chip two 6-characters HD66731A01TA0L straight tcp three 8-characters hd66731a01tb0l bending tcp four 10-characters hcd66731a01bp au-bumped chip four 10-characters
hd66730/hd66731 3 block diagram (hd66730) system interface ?serial ?8 bit ram data register (rdr: r9) busy flag (bf) index register (i dr) ram address counter (rar: r8) timing generator display data ram (ddram) 80 8 bits character generator ram (cgram) 208 bytes character generator rom for full-size character font (fcgrom) 506,880 bits (704 b 720 w) display attribute control circuit 71-bit latch circuit 71-bit shift register common driver lcd drive voltage selector oscillation circuit (cpg) control register (r0 to r7) v1 rs/cs * rw/sid e/sclk v cc gnd com1 to com24 osc1 osc2 8 8 8 8 7 7 8 8 11 8 4 segment ram (segram) 16 bytes cl1 cl2 m segd reset * segment driver seg1 to seg71 db0/sod cursol control circuit vci c1 c2 v5out2 v5out3 character generator rom for half-size character font (hcgrom) 9,216 bits (768 b 12 w) parallel/serial converter and scroll control circuit 12 12 25-bit shift register booster 12 coms com25/ comd 8 4 im address generator 12 7 3 db1 to db7 i/o buffer 12 v2 v3 v4 v5
hd66730/hd66731 4 pin arrangement (hd66730) seg7 seg6 seg5 seg4 seg3 seg2 seg1 coms com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25/comd v1 v2 v3 v4 v5 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 v cc reset * osc2 osc1 cl1 cl2 segd m rw/sid rs/cs * e/sclk im db0/sod db1 db2 db3 db4 db5 db6 db7 gnd vci c2 c1 v5out2 v5out3 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 seg56 seg57 seg58 seg59 seg60 seg61 seg62 seg63 seg64 seg65 seg66 seg67 seg68 seg69 seg70 seg71 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 hd66730 (top view) 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
hd66730/hd66731 5 tcp dimensions (hd66731ta0: three 8-characters) 0.24p (141?) = 33.60mm 0.8p (30?) = 23.2mm 0.24mm pitch 0.80mm pitch i/o, power supply lcd driver output dummy dummy com40 com20 seg96 seg1 coms com1 com19 dummy dummy nc v cc osc2 osc1 tesed reset * rw/sid rs/cs * e/sclk im db0/sod db1 db2 db3 db4 db5 db6 db7 gnd v ci c2 c1 v5out2 v5out3 v5 v4 v3 v2 v1 n c
hd66730/hd66731 6 tcp dimensions (hd66731tb0: four 10-characters) 0.20p (176?) = 35.0mm 0.8p (30?) = 23.2mm 0.20mm pitch 0.80mm pitch i/o, power supply lcd driver output dummy dummy com53 com45 com20 seg119 seg1 coms com1 com51 dummy dummy nc v cc osc2 osc1 tesed reset * rw/sid rs/cs * e/sclk im db0/sod db1 db2 db3 db4 db5 db6 db7 gnd v ci c2 c1 v5out2 v5out3 v5 v4 v3 v2 v1 nc com19 com46
hd66730/hd66731 7 the location of bonding pads (hd66730) 1 pin 128 pin type code hd66730 99 pin 35 pin 68 pin chip size (x y): coordinate: origin: pad size (x y): 7.48 6.46 mm 2 pad center chip center 100 100 m m 2 4 pin y x hcd66730 (unit: m) pin coordinate pin coordinate pin coordinate no. function x y no. function x y no. function x y 1 seg34 ?602 3012 31 seg64 ?522 ?183 61 c2 1896 ?959 2 seg35 ?984 3012 32 seg65 ?522 ?364 62 c1 2057 ?959 3 seg36 ?263 3012 33 seg66 ?522 ?544 63 v5out2 2219 ?959 4 seg37 ?522 3012 34 seg67 ?522 ?774 64 v5out3 2478 ?959 5 seg38 ?522 2782 35 seg68 ?522 ?984 65 v5 2782 ?984 6 seg39 ?522 2582 36 seg69 ?160 ?984 66 v4 3016 ?984 7 seg40 ?522 2341 37 seg70 ?860 ?984 67 v3 3253 ?984 8 seg41 ?522 2161 38 seg71 ?660 ?984 68 v2 3522 ?984 9 seg42 ?522 1981 39 v cc ?435 ?984 69 v1 3522 ?806 10 seg43 ?522 1801 40 reset* ?233 ?984 70 com25/d 3522 ?626 11 seg44 ?522 1621 41 osc2 ?063 ?984 71 com24 3522 ?445 12 seg45 ?522 1440 42 osc1 ?859 ?984 72 com23 3522 ?265 13 seg46 ?522 1260 43 cl1 ?689 ?984 73 com22 3522 ?085 14 seg47 ?522 1030 44 cl2 ?519 ?984 74 com21 3522 ?855 15 seg48 ?522 800 45 segd ?349 ?984 75 com20 3522 ?625 16 seg49 ?522 620 46 m ?179 ?984 76 com19 3522 ?444 17 seg50 ?522 439 47 rw/sid ?75 ?984 77 com18 3522 ?264 18 seg51 ?522 259 48 rs/cs* ?71 ?984 78 com17 3522 ?084 19 seg52 ?522 79 49 e/sclk ?67 ?984 79 com16 3522 ?54 20 seg53 ?522 ?01 50 im ?63 ?984 80 com15 3522 ?24 21 seg54 ?522 ?81 51 db0/sod ?46 ?984 81 com14 3522 ?43 22 seg55 ?522 ?62 52 db1 71 ?984 82 com13 3522 ?63 23 seg56 ?522 ?42 53 db2 287 ?984 83 com12 3522 ?3 24 seg57 ?522 ?22 54 db3 504 ?984 84 com11 3522 97 25 seg58 ?522 ?002 55 db4 721 ?984 85 com10 3522 277 26 seg59 ?522 ?182 56 db5 938 ?984 86 com9 3522 458 27 seg60 ?522 ?363 57 db6 1154 ?984 87 com8 3522 638 28 seg61 ?522 ?543 58 db7 1371 ?984 88 com7 3522 818 29 seg62 ?522 ?723 59 gnd 1533 ?984 89 com6 3522 998 30 seg63 ?522 ?939 60 vci 1730 ?959 90 com5 3522 1178
hd66730/hd66731 8 pin coordinate pin coordinate pin coordinate no. function x y no. function x y no. function x y 91 com4 3522 1409 104 seg9 2152 3012 117 seg22 ?91 3012 92 com3 3522 1639 105 seg10 1972 3012 118 seg23 ?71 3012 93 com2 3522 1819 106 seg11 1791 3012 119 seg24 ?51 3012 94 com1 3522 1999 107 seg12 1611 3012 120 seg25 ?31 3012 95 coms 3522 2179 108 seg13 1431 3012 121 seg26 ?12 3012 96 seg1 3522 2410 109 seg14 1251 3012 122 seg27 ?092 3012 97 seg2 3522 2590 110 seg15 1071 3012 123 seg28 ?272 3012 98 seg3 3522 2819 111 seg16 890 3012 124 seg29 ?452 3012 99 seg4 3522 3012 112 seg17 710 3012 125 seg30 ?632 3012 100 seg5 3222 3012 113 seg18 530 3012 126 seg31 ?813 3012 101 seg6 2942 3012 114 seg19 350 3012 127 seg32 ?993 3012 102 seg7 2662 3012 115 seg20 170 3012 128 seg33 ?173 3012 103 seg8 2332 3012 116 seg21 ?1 3012
hd66730/hd66731 9 the location of bonding pads (hd66731) seg88 seg89 seg90 seg91 seg92 seg93 seg94 seg95 seg96 seg97 seg98 seg99 seg100 seg101 seg102 seg103 seg104 seg105 seg106 seg107 seg108 seg109 seg110 seg111 seg112 seg113 seg114 seg115 seg116 seg117 seg118 seg119 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com32 com33 com34 com35 com36 com37 con38 com39 com40 com41 com42 com43 com44 com45 com53 v cc v cc v cc v cc v cc v1 v1 v2 v2 v3 v3 dummy5 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 coms com1 com2 com3 com4 com5 com6 com7 com8 com9 con10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com46 com47 com48 com49 com50 com51 dummy18 dummy17 dummy16 dummy15 dummy14 dummy13 seg87 seg86 seg85 seg84 seg83 seg82 seg81 seg80 seg79 seg78 seg77 seg76 seg75 seg74 seg73 seg72 seg71 seg70 seg69 seg68 seg67 seg66 seg65 seg64 seg63 seg62 seg61 seg60 seg59 seg58 seg57 seg56 seg55 seg54 seg53 seg52 seg51 seg50 seg49 seg48 seg47 seg46 seg45 seg44 seg43 seg42 seg41 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 srg32 seg31 seg30 seg29 dummy12 dummy11 dummy10 dummy9 dummy8 dummy7 dummy6 dummy1 dummy2 dummy3 osc2 osc1 testd reset * rw/sid rs/cs * e/sclk im db0/sod db1 db2 db3 db4 db5 db6 db7 gnd gnd gnd v ci v ci v ci c2 c2 c2 c1 c1 c1 v5out2 v5out2 v5out2 v5out3 v5out3 v5 v5 v5 v4 v4 dummy4 hd66731 (top view) hd66731 y x type code ?chip size ?coordinate ?origin ?au bumped distance ?bump size : 7.48 6.46mm 2 : pad center : chip center : 80 m (min.) : 100 m 50 m 99 157 158 98 39 38 1 221
hd66730/hd66731 10 pin coordinate pin coordinate pin coordinate no. function x y no. function x y no. function x y dummy3 ?202 ?984 45 com51 3474 ?621 92 seg22 3474 2255 1 osc2 ?926 ?984 46 com50 3474 ?541 93 seg23 3474 2335 2 osc1 ?722 ?984 47 com49 3474 ?460 94 seg24 3474 2416 3 testd ?543 ?984 48 com48 3474 ?379 95 seg25 3474 2497 4 reset * ?339 ?984 49 com47 3474 ?298 96 seg26 3474 2578 5 rw/sid ?135 ?984 50 com46 3474 ?218 97 seg27 3474 2658 6 rs/cs ?931 ?984 51 com19 3474 ?137 98 seg28 3474 2739 7 e/sclk ?727 ?984 52 com18 3474 ?056 dummy6 3474 3027 8 im ?523 ?984 53 com17 3474 ?75 dummy7 3202 3027 9 db0/sod ?306 ?984 54 com16 3474 ?95 dummy8 3066 3027 10 db1 ?090 ?984 55 com15 3474 ?14 dummy9 2930 3027 11 db2 ?73 ?984 56 com14 3474 ?33 dummy10 2794 3027 12 db3 ?56 ?984 57 com13 3474 ?52 dummy11 2658 3027 13 db4 ?39 ?984 58 com12 3474 ?72 dummy12 2522 3027 14 db5 ?23 ?984 59 com11 3474 ?91 99 seg29 2343 2963 15 db6 ? ?984 60 com10 3474 ?10 100 seg30 2262 2963 16 db7 211 ?984 61 com9 3474 ?29 101 seg31 2182 2963 17 gnd 373 ?971 62 com8 3474 ?49 102 seg32 2101 2963 18 gnd 509 ?971 63 com7 3474 ?68 103 seg33 2020 2963 19 gnd 645 ?971 64 com6 3474 ?7 104 seg34 1939 2963 20 vci 781 ?971 65 com5 3474 ? 105 seg35 1859 2963 21 vci 917 ?971 66 com4 3474 74 106 seg36 1778 2963 22 vci 1053 ?971 67 com3 3474 155 107 seg37 1697 2963 23 c2 1189 ?971 68 com2 3474 236 108 seg38 1616 2963 24 c2 1325 ?971 69 com1 3474 317 109 seg39 1536 2963 25 c2 1461 ?971 70 coms 3474 397 110 seg40 1455 2963 26 c1 1597 ?971 71 seg1 3474 559 111 seg41 1374 2963 27 c1 1733 ?971 72 seg2 3474 640 112 seg42 1293 2963 28 c1 1869 ?971 73 seg3 3474 720 113 seg43 1213 2963 29 v5out2 2005 ?971 74 seg4 3474 801 114 seg44 1132 2963 30 v5out2 2141 ?971 75 seg5 3474 882 115 seg45 1051 2963 31 v5out2 2277 ?971 76 seg6 3474 963 116 seg46 970 2963 32 v5out3 2413 ?971 77 seg7 3474 1043 117 seg47 890 2963 33 v5out3 2549 ?971 78 seg8 3474 1124 118 seg48 809 2963 34 v5 2685 ?971 79 seg9 3474 1205 119 seg49 728 2963 35 v5 2821 ?971 80 seg10 3474 1286 120 seg50 647 2963 36 v5 2957 ?971 81 seg11 3474 1366 121 seg51 567 2963 37 v4 3093 ?971 82 seg12 3474 1447 122 seg52 468 2963 38 v4 3229 ?971 83 seg13 3474 1528 123 seg53 405 2963 dummy4 3474 ?971 84 seg14 3474 1609 124 seg54 324 2963 dummy5 3474 ?699 85 seg15 3474 1689 125 seg55 244 2963 39 v3 3474 ?563 86 seg16 3474 1770 126 seg56 163 2963 40 v3 3474 ?427 87 seg17 3474 1851 127 seg57 82 2963 41 v2 3474 ?291 88 seg18 3474 1932 128 seg58 1 2963 42 v2 3474 ?155 89 seg19 3474 2012 129 seg59 ?9 2963 43 v1 3474 ?019 90 seg20 3474 2093 130 seg60 ?60 2963 44 v1 3474 ?883 91 seg21 3474 2174 131 seg61 ?41 2963
hd66730/hd66731 11 pin coordinate pin coordinate pin coordinate no. function x y no. function x y no. function x y 132 seg62 ?22 2963 158 seg88 ?474 2728 191 com21 ?474 ?7 133 seg63 ?02 2963 159 seg89 ?474 2647 192 com22 ?474 ?8 134 seg64 ?83 2963 160 seg90 ?474 2567 193 com23 ?474 ?79 135 seg65 ?64 2963 161 seg91 ?474 2486 194 com24 ?474 ?60 136 seg66 ?45 2963 162 seg92 ?474 2405 195 com25 ?474 ?40 137 seg67 ?25 2963 163 seg93 ?474 2324 196 com26 ?474 ?21 138 seg68 ?06 2963 164 seg94 ?474 2244 197 com27 ?474 ?02 139 seg69 ?87 2963 165 seg95 ?474 2163 198 com28 ?474 ?83 140 seg70 ?68 2963 166 seg96 ?474 2082 199 com29 ?474 ?63 141 seg71 ?048 2963 167 seg97 ?474 2001 200 com30 ?474 ?44 142 seg72 ?129 2963 168 seg98 ?474 1921 201 com31 ?474 ?25 143 seg73 ?210 2963 169 seg99 ?474 1840 202 com32 ?474 ?06 144 seg74 ?291 2963 170 seg100 ?474 1759 203 com33 ?474 ?86 145 seg75 ?371 2963 171 seg101 ?474 1678 204 com34 ?474 ?067 146 seg76 ?452 2963 172 seg102 ?474 1598 205 com35 ?474 ?148 147 seg77 ?533 2963 173 seg103 ?474 1517 206 com36 ?474 ?229 148 seg78 ?614 2963 174 seg104 ?474 1436 207 com37 ?474 ?309 149 seg79 ?694 2963 175 seg105 ?474 1355 208 com38 ?474 ?390 150 seg80 ?775 2963 176 seg106 ?474 1275 209 com39 ?474 ?471 151 seg81 ?856 2963 177 seg107 ?474 1194 210 com40 ?474 ?552 152 seg82 ?937 2963 178 seg108 ?474 1113 211 com41 ?474 ?632 153 seg83 ?017 2963 179 seg109 ?474 1032 212 com42 ?474 ?713 154 seg84 ?098 2963 180 seg110 ?474 952 213 com43 ?474 ?794 155 seg85 ?179 2963 181 seg111 ?474 871 214 com44 ?474 ?875 156 seg86 ?260 2963 182 seg112 ?474 79 215 com45 ?474 ?955 157 seg87 ?340 2963 183 seg113 ?474 709 216 com53 ?474 ?036 dummy13 ?522 3027 184 seg114 ?474 629 217 v cc ?474 ?169 dummy14 ?658 3027 185 seg115 ?474 548 218 v cc ?474 ?305 dummy15 ?794 3027 186 seg116 ?474 467 219 v cc ?474 ?441 dummy16 ?930 3027 187 seg117 ?474 386 220 v cc ?474 ?577 dummy17 ?066 3027 188 seg118 ?474 306 221 v cc ?474 ?713 dummy18 ?202 3027 189 seg119 ?474 225 dymmy2 ?474 ?984 dummy1 ?474 3027 190 com20 ?474 63
hd66730/hd66731 12 pin function (hd66730) table 1 pin functional description signal number of pins i/o device interfaced with function reset* 1 i acts as a reset input pin. the lsi is initialized during low level. refer to reset function. must be reset after power-on. im 1 i selects interface mode with the mpu; low: serial mode high: 8-bit bus mode rs/cs* 1 i mpu selects registers during bus mode: low: index register (write); status register (read) high: control register (write); ram data (read/write) acts as chip-select during serial mode: low: select (access enable) high: not selected (access disable) r w /sid 1 i mpu selects read/write during bus mode; low: write high: read inputs serial data during serial mode. e/sclk 1 i mpu starts data read/write during bus mode; inputs (receives) serial clock during serial mode. db1 to db7 7 i/o mpu seven high-order bidirectional tristate data bus pins. used for data transfer between the mpu and the hd66730. db7 can be used as a busy flag. open these pins during serial mode since these signals are not used. db0/ sod 1 i/o /o mpu the lowest bidirectional data bit (db0) during bus mode. outputs (transmits) serial data during serial mode. open this pin if reading (transmission) is not performed. seg1 to seg71 71 o lcd display data output signals for the segment extension driver. coms 1 o lcd acts as a common output signal for segment display. used to display icon and marks beside the character display. com1 to com24 24 o lcd acts as common output signals for character display. com15 tocom24 become non-selective waveforms when the duty ratio is 1/14. com25/ comd 1 o lcd/ extension driver acts as common output sign al (com25) for character display when ext2 bit is 0. acts as a common extension pulse signal (comd) when ext2 bit is 1. the pin is grounded after reset input is cleared. when this signal is used as comd, gnd 3 v5 must be maintained.
hd66730/hd66731 13 table 1 pin functional description (cont. hd66730) signal number of pins i/o device interfaced with function cl1 1 o extension driver outputs the latch pulse of segment extension driver.cam also be used as a shift clock of common extention driver. exters tristate when both ext1 and ext2 are 0. cl2 1 o extension driver outputs shift clock of segment extension driver. can also be used as a common extension driver latch clock. enters tristate when both ext1 and ext2 are 0. segd 1 o extension driver outputs data of extension driver. data after the 72nd dot is output. enters tristate when ext1 bit is 0. m 1 o extension driver acts as an alternating current signal of extension driver. enters tristate when both ext1 and ext2 bits are 0. v1 to v5 5 power supply power supply for lcd drive v cc ?v5 = 15v (max) v cc /gnd 2 power supply v cc : +2.4v to +5.5v, gnd: 0v osc1/ osc2 2 oscillation resistor/ clock when crystal oscillation is performed, an external resistor must be connected. when the pin input is an external clock, it must be input to osc1. vci 1 i inputs voltage to the booster to generate the liquid crystal display drive voltage. vci is reference voltage and power supply for the booster. vci: 1.0v to 5.0v v cc . v5out2 1 o v5 pin/ booster capacitor voltage input to the vci pin is boosted twice and output. when the voltage is boosted three times, a capacitor with the same capacitance as that of c1?2 should be connected here. v5out3 1 o v5 pin voltage input to the vci pin is boosted three times and output. c1/c2 2 booster capacitor external capacitor should be connected here when using the booster.
hd66730/hd66731 14 pin function (hd66731) table 2 pin functional description signal number of pins i/o device interfaced with function reset* 1 i acts as a reset input pin. the lsi is initialized during low level. refer to reset function. must be reset after power-on. im 1 i selects interface mode with the mpu; low: serial mode high: 8-bit bus mode rs/cs* 1 i mpu selects registers during bus mode: low: index register (write); status register (read) high: control register (write); ram data (read/write) acts as chip-select during serial mode: low: select (access enable) high: not selected (access disable) r w /sid 1 i mpu selects read/write during bus mode; low: write high: read inputs serial data during serial mode. e/sclk 1 i mpu starts data read/write during bus mode; inputs (receives) serial clock during serial mode. db1 to db7 7 i/o mpu seven high-order bidirectional tristate data bus pins. used for data transfer between the mpu and the hd66731. db7 can be used as a busy flag. open these pins during serial mode since these signals are not used. db0/ sod 1 i/o /o mpu the lowest bidirectional data bit (db0) during bus mode. outputs (transmits) serial data during serial mode. open this pin if reading (transmission) is not performed. seg1 to seg119 119 o lcd display data output signals for the segment extension driver. coms 1 o lcd acts as a common output signal for segment display. used to display icon and marks beside the character display. com1 to com51 51 o lcd acts as common output signals for character display. com14 acts as same as coms when 1/14 duty. com27 acts as same as coms when 1/27 duty. com40 acts as same as coms when 1/40 duty. unused common pins output non-selective waveforms. com53 1 o lcd acts as common output signal for segment display when 1/53 duty. the waveform is same as coms. this com53 outputs non-selective waveform when another duty.
hd66730/hd66731 15 table 2 pin functional description (cont. hd66731) signal number of pins i/o device interfaced with function v1 to v5 5 power supply power supply for lcd drive v cc ?v5 = 15v (max) v cc /gnd 2 power supply v cc : +2.4v to +5.5v, gnd: 0v osc1/ osc2 2 oscillation resistor/ clock when crystal oscillation is performed, an external resistor must be connected. when the pin input is an external clock, it must be input to osc1. vci 1 i inputs voltage to the booster to generate the liquid crystal display drive voltage. vci is reference voltage and power supply for the booster. vci: 1.0v to 5.0v v cc . v5out2 1 o v5 pin/ booster capacitor voltage input to the vci pin is boosted twice and output. when the voltage is boosted three times, a capacitor with the same capacitance as that of c1?2 should be connected here. v5out3 1 o v5 pin voltage input to the vci pin is boosted three times and output. c1/c2 2 booster capacitor external capacitor should be connected here when using the booster. testd 1 o test pin. must be left disconnected. dummy1 to dummy18 18 dummy pads. these pads are electrically floating level.
hd66730/hd66731 16 function description system interface the hd66730/1 has two system interfaces: a synchronized serial one and an 8-bit bus. both are selected by the im pin. the hd66730/1 has five types of 8-bit registers: an index register (idr), status register (str), various control registers, ram address register (rar), and ram data register (rdr). the index register (idr) selects control registers, the ram address register (rar) or the ram data register (rdr) for performing data transfer. the status register (str) indicates the internal state of the system. various control registers store display control data here. the ram address register (rar) stores the address data of display data ram (ddram), character generator ram (cgram), and segment ram (segram). the ram data register (rdr) temporarily stores data to be written into ddram, cgram, or segram. data written into the rdr from the mpu is automatically written into ddram, cgram, or segram by internal operations. the rdr is also used for data storage when reading data from ddram, cgram, or segram. here, when address information is written into the rar, data is read and then stored into the rdr from ddram, cgram, or segram by internal operations. data transfer between the mpu is then completed when the mpu reads the rdr. after this read, data in ddram, cgram, or segram stored at the next address is sent to the rdr at the next data read from the mpu. these registers can be selected by the register select signal (rs) and the read/write signal (r/w) in the 8-bit bus interface, and by the rs bit and r/w bit of start-byte data in the synchronized serial interface. busy flag when the busy flag is 1, the hd66730/1 is in internal operation mode, and only the status register (str) can be accessed. the busy flag (bf) is output from bit 7 (db7). access of other registers can be performed only after confirming that the busy flag is 0. ram address counter (rar) the ram address counter (rar) provides addresses for accessing ddram, cgram, or segram. when an initial address value is written into the ram counter (rar), the rar is automatically incremented or decremented by 1. note that a control register specifies which ram (ddram, cgram, segram) to select.
hd66730/hd66731 17 table 3 register selection rs r/ w operation 0 0 idr write 0 1 str read 1 0 control register write, ram address register (rar) write, and ram data register (rdr) write 1 1 ram data register (rdr) read
hd66730/hd66731 18 display data ram (ddram) display data ram (ddram) stores character codes and display attribute codes for displaying data. a full-size font is displayed using two bytes, and a half-size font is displayed using one byte. since the ram capacity is 80 bytes, 40 full-size characters or 80 half-size characters can be stored. ddram displays only that data stored within the range corresponding to the number of display columns. data stored outside the range is ignored. refer to combined display of full-size and half-size characters for details on character codes stored in ddram. the relationship between ddram addresses and lcd display position depends on the number of display lines (1 line/2 lines/4 lines). execution of the display-clear instruction writes h'a0 corresponding to the half-size character for ?pace throughout ddram. note: the hd66730/1 performs display by reading character codes from the ddram according to the number of display columns set by the control register. in particular, reading from the ddram begins at the position corresponding to the rightmost character as set by the maximum number of display columns. this means that one byte of a two-byte full-size character code should not be set in a position exceeding the maximum number of display columns. for example, do not write a full- size code (2 bytes) in the 12th and 13th byte when the display is set for six characters. 1-line display (nl1/0 = 00) 80 bytes of consecutive addresses from h'00 to h'4f are allocated for ddram addresses. when there are fewer than 40 display characters (at full size), only the number of display characters specified by nc1/0 are displayed starting from h'00 in the ddram. for example, 12 bytes of addresses from h'00 to h'0b are used when a 6-character display (nc1/0 = 00) is performed using one hd66730; addresses from h'0c on are ignored. in this case, do not write a full-size code into bytes h'0b and h'0c because a half-size character may be displayed. see figure 1 for a 1-line display. 2-line display (nl1/0 = 01) the first line in the ddram address is displayed for the 40 bytes of addresses from h'00 to h'27, and the second line is displayed for the 40 bytes of addresses from h'40 to h'67. when there are fewer than 20 display characters (at full size), only the number of display characters specified by nc1/0 will be displayed starting from the leftmost address of the ddram. for example, 24 bytes of addresses from h'00 to h'0b and h'40 to h'4b are used when a 6-character display (nc1/0 = 00) is performed using one hd66730. addresses from h'0c and h'4c on are ignored. see figure 2 for a 2-line display. 4-line display (nl1/0 = 11) the first line in the ddram address is displayed from h'00 to h'13, the second line from h'20 to h'33, the third line from h'40 to h'53, and the fourth line from h'60 to h'73. for a 6-character display (nc1/0 = 00) (at full-size), only 12 bytes from the leftmost address of ddram are displayed. see figure 3 for a 4-line display.
hd66730/hd66731 19 display position ddram address 00 01 02 03 04 05 06 0a 0b 07 123456 09 08 6-character display setting (nc1/0 = 00) display position ddram address 00 01 02 03 04 05 06 0a 0b 07 123456 09 08 20-character display setting (nc1/0 = 01) 26 27 20 display position ddram addres 00 01 02 03 04 05 06 0a 0b 07 123456 09 40-character display setting ( nc1/0 = 10 ) 4e 4f 40 4c 4d 39 24 25 19 08 figure 1 1-line display (nl1/0 = 00) display position 1st line ddram address 00 01 02 03 04 05 06 0a 0b 07 123456 09 08 6-character display setting (nc1/0 = 00) display position 1st line ddram address 00 01 02 03 04 05 06 0a 0b 07 123456 09 08 10-character display setting (nc1/0 = 01) 12 13 10 display position 1st line ddram address 00 01 02 03 04 05 06 0a 0b 07 123456 09 08 20-character display setting (nc1/0 = 10) 26 27 20 24 25 19 10 11 9 40 41 42 43 44 45 46 4a 4b 47 49 48 40 41 42 43 44 45 46 4a 4b 47 49 48 52 53 50 51 40 41 42 43 44 45 46 4a 4b 47 49 48 66 67 64 65 2nd line ddram address 2nd line ddram address 2nd line ddram address figure 2 2-line display (nl1/0 = 01) display position 1st line ddram address 00 01 02 03 04 05 06 0a 0b 07 123456 09 08 6-character display setting (nc1/0 = 00) display position 1st line ddram address 00 01 02 03 04 05 06 0a 0b 07 123456 09 08 10-character display setting (nc1/0 = 01) 12 13 10 10 11 9 20 21 22 23 24 25 26 2a 2b 27 29 28 32 33 30 31 2nd line ddram address 2nd line ddram address 3rd line ddram address 4th line ddram address 40 41 42 43 44 45 46 4a 4b 47 49 48 52 53 50 51 3rd line ddram address 60 61 62 63 64 65 66 6a 6b 67 69 68 72 73 70 71 4th line ddram address 60 61 62 63 64 65 66 6a 6b 67 69 68 40 41 42 43 44 45 46 4a 4b 47 49 48 20 21 22 23 24 25 26 2a 2b 27 29 28 0c 0d 7 2c 2d 4c 4d 6c 6d 0e 0f 8 2e 2f 4e 4f 6e 6f figure 3 4-line display (nl1/0 = 11)
hd66730/hd66731 20 character generator rom for a full-size font (fcgrom) the character generator rom for a full-size font (fcgrom) generates 3,840 11 12 dot full-size character patterns from a 12-bit character code. this includes 2,965 kanji according to the jis level-1 kanji set and 524 jis non-kanji. table 4 shows the relationship between character codes set in ddram and full-size font patterns. refer to combined display of full-size and half-size characters for the relationship between jis codes and the character codes to be set in the ddram. character generator rom for a half-size font (hcgrom) the character generator rom for a half-size font (hcgrom) generates 128 6 12 dot character patterns from 7-bit character codes. a half-size font (alphanumeric characters and symbols) can be displayed together with a full-size font. refer to combined display of full-size and half-size characters for details. character generator ram (cgram) the character generator ram (cgram) allows the user to display arbitrary full-size font patterns. it can display 8 12 13 dot fonts. this ram can also display double-size characters and figures by combining multiple cgram fonts. specify character codes from h'000 to h'007 in a full size of character code when displaying font patterns stored in the cgram. segment ram (segram) the segment ram (segram) is used to control icons and marks in segment units by the user program. bits in segram corresponding to segments to be displayed are directly set by the mpu, regardless of the contents of ddram and cgram. the segram is read and displayed when the coms output pin is selected. up to 71 icons can be displayed using a single hd66730. up to 96 icons can be displayed by expanding the drivers on the segment side. segram data is stored in eight bits. the lower six bits control the display of each segment, and the upper two bits control segment blinking. hd66731 can display 96 icons without the expanding driver.
hd66730/hd66731 21 timing generator the timing generator generates timing signals for the operation of internal circuits such as ddram, fcgrom, hcgrom, cgram, and segram. ram read timing for display and internal operation timing for mpu access are generated separately to avoid interference. this prevents undesirable interferences, such as flickering, in areas other than the display area when writing data to ddram, for example. the timing generator of hd66730 generates interface control signals cl1, cl2, m, and comd-output of extension drivers for a extension configuration. display attribute controller the display attribute controller displays white/black inverse, blinking, and white/black inverse blinking for a full size font in fcgrom according to the attribute code set in the ddram. refer to display attribute designation for details. fonts in cgram and bit patterns in segram control display attributes using the upper two bits (bits 7 and 6) in each display-pattern data. cursor control circuit the cursor control circuit is used to produce a cursor on a displayed character corresponding to the ddram address set in the ram address counter (rar). cursors can be chosen from three types: 12th raster-row cursor that is displayed only on the 12th raster-row of each font; blink cursor that periodically displays the whole font in black and white and black inverted cursor that periodically displays the font in white and black (see figure 9). note that when the ram address counter (rar) is selecting cgram or segram, a cursor would be generated at that address, however, it does not have any meaning. note: one display line consists of 13 raster-rows. smooth scroll control circuit the smooth scroll control circuit is used to perform a smooth-scroll in units of dots. when the number of characters to be displayed is greater than that possible at one time in the liquid crystal module, this horizontal smooth scroll can be used to display characters in an easy-to-read manner for each line. refer to horizontal smooth scroll for details for each line.
hd66730/hd66731 22 liquid crystal display driver circuit the liquid crystal display driver circuit of hd66730 consists of 26 common signal drivers and 71 segment signal drivers. hd66731 has 54 common signal drivers and 119 segment signal drivers. when the liquid crystal driver duty ratio is set by a program, the necessary common signal drivers output drive waveforms and the remaining common drivers output non-selected waveforms. in addition, drivers can be expanded on the common and segment sides through register settings. display pattern data is sent serially through a shift register and latched when all needed data has arrived. the latched data then enables the lcd driver to generate drive waveform outputs. this serial data is sent from the display pattern that corresponds to the last address of the ddram and is latched when the character pattern of the display data corresponding to the first address enters the internal shift register. booster the booster outputs a voltage that is two or three times higher than the reference voltage input from pin vci. since the lcd voltage can be generated from the lsi operation power supply, this circuit can operate with a single power supply. refer to power supply for liquid crystal display drive for details. oscillator the hd66730/1 performs r-c oscillation by adding a single external oscillation resistor. the oscillation frequency corresponding to display size and frame frequency can be adjusted by changing the oscillation resistor. refer to oscillator for details.
hd66730/hd66731 23 table 4 relationship between full-size character code and kanji upper / lower
hd66730/hd66731 24 table 4 relationship between full-size character code and kanji (cont) upper / lower
hd66730/hd66731 25 table 4 relationship between full-size character code and kanji (cont) upper / lower
hd66730/hd66731 26 table 4 relationship between full-size character code and kanji (cont) upper / lower
hd66730/hd66731 27 table 5 relationship between full-size character code and non-kanji upper / lower
hd66730/hd66731 28 table 6 relationship between half-size character code and character pattern (rom code: a00) (space) xxxx 000 lower (3 bits) upper (4 bits) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 xxxx 001 xxxx 010 xxxx 011 xxxx 100 xxxx 101 xxxx 110 xxxx 111

hd66730/hd66731 62 relationship between character codes (ddram), cgram addresses, and display characters full size character codes h'000 to h'007 can be used to access 8 character patterns in the cgram. since each character pattern can be displayed up to 12 13 dots, cgram patterns can be displayed immediately next to each other (to the right, left, top, or bottom) without any character spaces between them. table 6 shows the correspondence between cgram addresses and full-size character codes for access of the cgram by the mpu. table 7 relationship between character codes (ddram), cgram addresses, and display characters c11 c3 c7 c6 c5 000000000 0 0 0 a6 a5 a4 000 a3 a2 a1 000 a7 0 d7d6 a d5 0 d4 0 d3 0 d2 0 d1 0 d0 0 d7 a d6 a d5 0 d4 0 d3 0 d2 0 d1 0 d0 0 a0 = 0 a0 = 1 cgram data a a 0 11 1 1 1 aa1 111 00 a a 0 1 00 00 aa 000 1 00 a a 0 1 00 00 aa 000 1 00 a a 0 1 00 00 aa 000 1 00 a a 0 1 00 00 aa 000 1 00 a a 0 111 11 aa1 111 00 a a 0 1 00 00 aa 000 1 00 a a 0 1 00 00 aa 000 1 00 a a 0 1 00 00 aa 000 1 00 a a 0 1 00 00 aa 000 1 00 a a 0 111 11 aa1 111 00 a a 0 000 00 aa 0 000 00 a a 0 000 0 1aa 0 000 00 a a 0 000 00 aa 1 000 00 a a 0 111 11 aa1 111 00 a a 0 000 00 aa 0 000 00 a a 00 1 000 aa 00 1 000 a a 00 1 000 aa 00 1 000 a a 00 1 000 aa 00 1 000 a a 000 1 00 aa 0 1 00 00 a a 000 1 00 aa 0 1 00 00 a a 000 1 00 aa 0 1 00 00 a a 0 000 00 aa 0 000 00 a a 1 111 11 aa 1 111 1 0 a a 0 000 00 aa 0 000 00 a 0 000 0 001 0 010 0 011 01 00 01 01 01 10 01 11 1 000 1 001 1 010 1 011 1 100 01 0 000 0 0 001 0 010 0 011 01 00 01 01 01 10 01 11 1 000 1 001 1 010 1 011 1 100 000000000 00 1 a 00 1 00 aa 0 1 000 a a 0 1 00 0 1aa 00 1 00 a a 0 1 00 11 aa 00 1 00 a a1 000 0 1aa 000 1 0 a a 1 000 0 1 aa 000 1 0 a a1 000 0 1aa 000 1 0 a a 1 000 0 1 aa 000 1 0 a a1 000 0 1aa 000 1 0 a a1 000 0 1aa 000 1 0 a a1 00 0 1aa 00 1 00 a a 0 1 00 0 1aa 00 1 00 a a 00 1 0 11 aa 000 a a 0 000 00 aa 0 000 00 a 110 000 1 0 001 0 010 0 011 01 00 01 01 01 10 0 111 1 000 1 00 1 1 010 1 01 1 1 100 000000000 1 1 1 cgram address character code character pattern (1) character pattern (2) character pattern (8) 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0
hd66730/hd66731 63 notes: 1. cgram is selected when the upper 9 bits (c3 to c11) of the full size character codes are 0. in this case, the lower 3 bits (c0 to c2) of the character code correspond to bits 5 to 7 (a5 to a7) (3 bits: 8 types) in the cgram address. 2. cgram address bits 1 to 4 (a1 to a4) designate the character pattern line position. the 12th line is the cursor position and its display is formed by a logical or with the cursor. 3. cgram address 0 (a0) corresponds to the left-half and right-half of a full-size character pattern. 4. the character data is stored with the rightmost character element in bit 0 (lsb), as shown in the table above. pattern produced by bits 0 to 5 is displayed and 13 raster-rows are displayed together. thus, an arbitrary character pattern consisting of 12 13 dots can be displayed. 5. a set bit in the cgram data corresponds to display selection, and 0 to non-selection. 6. the upper two bits (aa) of cgram data indicate the display attribute for the lower 6-bit pattern. in this case, display attributes specified for the ddram during full-size character display is disabled. when these upper two bits are 00, the cgram pattern is simply displayed as set; when 01, the pattern reverses (black/white), when 10, the pattern blinks; and when 11, the pattern reverses and blinks.
hd66730/hd66731 64 relationship between segram addresses and display patterns segram data is displayed when the select level of the coms pin is output. since segram data does not depend on character code data in ddram, and does not undergo horizontal smooth scroll, it can be used to display icon and marks. the following shows the relationship between segram addresses and segment output pins. table 8 relationship between segram addresses and display patterns b1 b0 seg1 seg7 b1 b0 seg13 b1 b0 seg19 b1 b0 seg25 b1 b0 seg31 b1 b0 seg37 b1 b0 seg43 b1 b0 0 0 0 1 0 0 0 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 1 1 a0 a1 a2 d7 d6 d5 segram address segram data blinking control pattern on/off 0 0 0 0 0 0 0 0 a3 seg61 b1 b0 seg67 b1 b0 seg73 b1 b0 seg79 b1 b0 seg85 b1 b0 seg91 b1 b0 0 0 0 1 0 0 0 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 seg49 b1 b0 seg55 seg2 seg8 seg14 seg20 seg26 seg32 seg38 seg44 d4 seg62 seg68 seg74 seg80 seg86 seg92 seg50 seg56 seg3 seg9 seg15 seg21 seg27 seg33 seg39 seg45 d3 seg63 seg69 seg75 seg81 seg87 seg93 seg51 seg57 seg4 seg10 seg16 seg22 seg28 seg34 seg40 seg46 d2 seg64 seg70 seg76 seg82 seg88 seg94 seg52 seg58 seg5 seg11 seg17 seg23 seg29 seg35 seg41 seg47 d1 seg65 seg71 seg77 seg83 seg89 seg95 seg53 seg59 seg6 seg12 seg18 seg24 seg30 seg36 seg42 seg48 d0 seg66 seg72 seg78 seg84 seg90 seg96 seg54 seg60 b1 b0 notes: 1. seg1 to seg71 are pin numbers of the segment output driver of the hd66730. pin seg1 is positioned on the left edge of the display. segments from seg72 on are displayed by extension drivers. after seg 96, display is performed from seg1 again. 2. the lower six bits (d0 to d5) indicate display on/off for of each segment. a bit setting of 1 selects display while 0 selects no display. 3. pattern blinking of the lower six bits is controlled by the upper two bits (d6 and d7) of segram data. when the upper two bits (b0 and b1) are 10, segments whose corresponding bits in the lower 6 bits are set to 1 will blink on the display. when the upper two bits (b0 and b1) are 01, only the bit-5 pattern can blink. do not attempt to set the upper two bits (b0 and b1) to 11 (setting is prohibited).
hd66730/hd66731 65 register functions outline data can be written from the mpu to the internal control registers and internal ram of the hd66730/1 via an 8-bit bus interface or a serial interface. there are five types of internal control registers, as follows (details are described later): index register: selects and designates which control register the mpu is to access status register: indicates the internal state control registers: designates display control ram address register: sets an address for accessing the various rams ram data register: receives and transmits data to and from the various rams table 17 shows the instruction list and the number of execution cycles of each instruction after performing register setting. instructions that perform data transfer with the ram data register tend to be used the most. however, auto-incrementation by 1 (or auto decrementation by 1) of internal hd66730/1 ram addresses after each data write can lighten the program load on the mpu. note that when an instruction is being executed (internal operations are being performed), only the busy flag in the status register can be read. since the busy flag is 1 during execution, the mpu should check this value before accessing a register. when accessing a register without checking the busy flag, an interval longer than the instruction execution time is needed before the next access. refer to table 17 instruction registers, for instruction execution times. when rewriting ddram, character display will momentarily breakdown if the data (character codes) that is being rewritten is also being read by the system for display. for this reason, check the display read line position (nf) and the display read raster-row position (lf) in the status register (sr), and rewrite a ddram line that is not being read and displayed.
hd66730/hd66731 66 functional description index register (ir) the index register (figure 4) designates control registers (r0 to r7), ram address register (rar: r8), and ram data register (rdr: r9). the register number must be set between addresses 0000 to 1001 in binary digits. note that if address 1111 is set, the test register will be selected. addresses 1010 to 1110 are ignored. r/w 0 rs 0 db7 0000id3id2id1 db0 id0 figure 4 index register
hd66730/hd66731 67 status register (st) the status register (figure 5) includes the busy flag (bf), display line bits (nf1/0), and display raster-row bits (lf0 to lf3). if bf is 1, an instruction is being executed, and another instruction will not be accepted during this time. any attempt to write data to a register at this time is ignored. rasters-rows are driven one at a time according to specific timing to perform liquid crystal display. bits nf1 and nf0 indicate display lines, and bits lf3 to lf0 indicate the raster-row in a line. if character display degenerates when rewriting ddram, rewrite only those display lines that are not currently being read out by the system for display. during segment display, the next state of the last raster-row in the character display is read out. table 9 display state according to nf1 and nf0 nf1 nf0 display state 0 0 displaying the first line 0 1 displaying the second line 1 0 displaying the third line 1 1 displaying the fourth line table 10 display state according to lf3 to lf0 lf3 lf2 lf1 lf0 display state 0 0 0 0 displaying the first raster-row 0 0 0 1 displaying the second raster-row 0 0 1 0 displaying the third raster-row 0 0 1 1 displaying the fourth raster-row 1 1 0 0 displaying the 13th raster-row r/w 1 rs 0 db7 bf nf1 nf0 0 lf3 lf2 lf1 db0 lf0 figure 5 status register
hd66730/hd66731 68 entry mode register (r0) the entry mode register (figure 6) includes bits i/d, rm1, and rm0. i/d: increments (i/d = 1) or decrements (i/d = 0) the ddram address by 1 when a character code is written into or read out from the ddram. when the ddram address is incremented by 1, the cursor or blinking will also shift to the right. this applies to both cgram and segram. rm1/0: selects ddram, cgram, or segram for access (table 10). table 11 ram selection by rm1 and rm0 rm1 rm0 selected ram 0 0/1 display data ram (ddram) 1 0 character generator ram (cgram) 1 1 segment ram (segram) r/w 0 rs 1 db7 00000i/drm1 db0 rm0 figure 6 entry mode register
hd66730/hd66731 69 function set register (r1) the function set register (figure 7) includes bits bst, ext2, ext1, dt1, dt0, and dcl. bst: when bst is 1, the booster starts to operate. when the lcd voltage is external, set bst to 0 to stop operation of the internal booster. in addition, the consumption current can be suppressed by stopping the booster when entering standby mode without display. ext2/1: extends the common driver and segment driver of hd66730. set ext2 to 1 to extend the driver to the common side if the duty ratio is 1/40 or 1/53. extend the driver to the segment side by setting ext1 to 1 when displaying 7 or more digits (of full size) in the horizontal direction. ddram capacity is 80 bytes. when the hd66731, these ext2/1 bits must be set to 1. dt1/0: selects the duty ratio of the lcd (table 11). although this bit can be set separately from the display line designation (nl1/0), the duty ratio must be selected so that it will be smaller than the number of display lines. dcl: when dcl is 1, the display is cleared by writing the code for half-size space (h'a0) into all ddram addresses. then h'00 is written into the ram address counter (rar) and the ddram is selected. the character code for character code h'a0 must be a blank pattern when rewriting hcgrom used for half-size characters. cursor control register (r2) the cursor control register includes bits chm, c, cm1, and cm0. chm: when chm is set to 1, ddram is selected, the ram address counter (rar) is set to 0, and the cursor home instruction is executed. the contents of ddram do not change. the cursor or blinking moves to the left edge of the display (the left edge of the first line if two lines are displayed). c: when c = 1, cursor display is turned on. the cursor is displayed at the position corresponding to the count value of the ram address counter (rar). to set data in the rar, set the index register (idr) to 1000 to select it, and modify the data in the rar. note that the ram address counter (rar) automatically increments (decrements) when the ram is accessed, and the cursor will move accordingly. cm1/0: selects cursor display mode (table 12 and figure 9). the blinking frequency (cycle) of the blink cursor and the white/black inverted cursor has 64 frames.
hd66730/hd66731 70 table 12 duty drive ratio dt1 dt0 duty drive ratio 0 0 1/14 duty drive 0 1 1/27 duty drive 1 0 1/40 duty drive 1 1 1/53 duty drive table 13 cursor mode selection cm1 cm0 selected cursor mode 0 0 12th raster-row cursor 0 1 blink cursor 1 0/1 white/black inverted cursor r/w 0 rs 1 db7 0 bst ext2 ext1 dt1 dt0 0 db0 dcl figure 7 function set register r/w 0 rs 1 db7 0000 chm c cm1 db0 cm0 figure 8 cursor control register
hd66730/hd66731 71 alternating display i) 12th-raster-row display example ii) blink display example iii) normal display example alternating display cursor white/black inverted display example figure 9 cursor display examples
hd66730/hd66731 72 display control register 1 (r3) the display control register 1 (figure 10) includes bits st, dc, and ds. st: when st is 1, the display control register 1 enters the standby mode. the internal operation clock is divided into 32. data cannot be displayed on the lcd panel, however, the consumption current can be suppressed during the standby mode. note that the register setting value and the data inside the ram are maintained. dc: when dc is 1, the character display is turned on. ds: when ds is 1, the segment display is turned on. bit ds can selectively display marks. display control register 2 (r4) nc1/0: selects the display character in the horizontal direction. when performing a horizontal smooth scroll, set the number of display characters larger than the actual number of liquid crystal drive characters. when the frame frequency (cycle) is stable, the operation frequency is proportional to the display characters. operation frequency must be suppressed by setting the number of display character as small as possible because the consumption current is proportional to the operation frequency. refer to oscillator for details. nl1/0: sets the number of display lines. set the number of display lines larger than the duty drive ratio (dt1/0). do not set 10 to these bits. table 13 indicates the settings of the display lines. table 14 display control register 2 setting display lines display characters: nc1/0 nl1/0 00 01 10 00 1-line 6 characters 1-line 20 characters 1-line 40 characters 01 2-line 6 characters 2-line 10 characters 2-line 20 characters 10 setting is inhibited. 11 4-line 6 characters 4-line 10 characters 4-line 10 characters r/w 0 rs 1 db7 0 0 0 0 0 st dc db0 ds figure 10 display control register 1 r/w 0 rs 1 db7 0 0 0 nc1 nc0 0 nl1 db0 nl0 figure 11 display control register 2
hd66730/hd66731 73 scroll control register 1 (r5) the scroll control register 1 (figure 12) includes bits sn1, sn0, sl3, sl2, sl1, and sl0. sn1/0: selects the starting line to be displayed. when sn1/0 shows 00, display begins from the first line. when sn1/0 shows 01, 10, 11, display begins from the second, third, or fourth line, respectively. use these bits within the display line setting (nl1/0). sn can be used to display a smooth scroll and ddram memory bank switching. sl0 to sl3: selects the scroll starting raster-row of the line set by the start display line (sl1/0). when these bits show 0000, a display line starting from the head raster-row (first raster-row) is displayed and can be set to 1100 (13th raster-row) showing the last raster-row. a vertical smooth scroll can be performed by sequentially incrementing the first raster-row. refer to vertical smooth scroll for details. note that bits sl0 to sl3 that are set to a value above 1100 will not operate correctly. scroll control register 2 (r6) the scroll control register 2 (figure 13) includes bits ps1, ps0, se4, se3, se2, and se1. ps1/0: selects the partial smooth scroll mode. when ps1/0 bits are 00, all characters scroll horizontally across the display. when bits ps1/0 are 01, only the leftmost character is fixed and the remaining characters perform horizontal smooth scroll display. when bits ps1/0 are 10, the two leftmost bits, and when 11, the three leftmost characters are fixed and the remaining characters perform horizontal smooth scroll refer to partial smooth scroll for details. se1 to se4: these bits enable a dot scroll in display lines designated by scroll control register 3 (r7). when bit se is 1, the first line is scrolled according to scroll control register 3 (r7). when se2 is 1, the second line scrolls independently, when se3 is 1, the third line scrolls independently, when se4 is 1, the fourth line scrolls independently. scrolling multiple lines at the same time is also possible. r/w 0 rs 1 db7 0 sn1 sn0 0 sl3 sl2 sl1 db0 sl0 figure 12 scroll control register 1 r/w 0 rs 1 db7 0 0 ps1 ps0 se4 se3 se2 db0 se1 figure 13 scroll control register 2
hd66730/hd66731 74 scroll control register 3 (r7) the scroll control register 3 (figure 14) includes bits sq5, sq4, sq3, sq2, sq1, and sq0. sq0 to sq5: these bits designate the number of dots to be horizontally scrolled to the left on the panel. horizontal smooth scroll can be performed for any number of dots between 1 and 48 inclusive by using the non-display ddram area. when these bits are 000000, scrolling is not performed. when these bits are 110000, 48 dots are scrolled to the left. if these bits are set to a value above 110000, 48 dots are still scrolled. refer to horizontal smooth scroll for details. ram address register (r8) the ram address register (figure15) initially contains the ram address at which incrementation (decrementation) starts. ram selection bits (rm1/0) in the entry mode register (r0) select which ram to access (ddram/cgram/segram). when ddram (rm1/0 = 00) is selected, address allocation differs according to the number of display lines, but in all cases the most significant bit (ra7) is ignored. during a 1-line display (nl1/0 = 00), addresses h'00 to h'4f are allocated to that line. during a 2-line display, addresses h'00 to h'27 are allocated to the first line, and addresses h'40 to h'67 are allocated to the second line. during a 4-line display, addresses h'00 to h'13 are allocated to the first line, h'20 to h'33 to the second , h'40 to h'53 to the third, and h'60 to h'73 to the fourth. see table 14. when cgram (rm1/0 = 10) is selected, addresses h'00 to h'19 are allocated to the first character and addresses h'20 to h'39 are allocated to the second character, and so on (table 15). the setting of addresses between characters (example: h'1a to h'1f) is ignored here. when segram is selected (rm1/0 = 11), addresses h'0 to h'f are allocated to the ram and the upper four bits (r4 to r7) are ignored (table 16). r/w 0 rs 1 db7 0 0 sq5 sq4 sq3 sq2 sq1 db0 sq0 figure 14 scroll control register 3 r/w 0 rs 1 db7 ra7 ra6 ra5 ra4 ra3 ra2 ra1 db0 ra0 figure 15 ram address register
hd66730/hd66731 75 table 15 ddram address allocation displayed lines 1-line display (nl1/0 = 00) 2-line display (nl1/0 = 01) 4-line display (nl1/0 = 00) first line h'00 to h'4f h'00 to h'27 h'00 to h'13 second line h'40 to h'67 h'20 to h'33 third line h'40 to h'53 fourth line h'60 to h'73 table 16 cgram address allocation displayed character cgram address first character h'00 to h'19 second character h'20 to h'39 third character h'40 to h'59 fourth character h'60 to h'79 fifth character h'80 to h'99 sixth character h'a0 to h'b9 seventh character h'c0 to h'd9 eighth character h'e0 to h'f9 table 17 segram address allocation displayed segment segram address seg1 to seg6 h'0 seg7 to seg12 h'1 seg13 to seg18 h'2 seg19 to seg24 h'3 seg25 to seg30 h'4 seg31 to seg36 h'5 seg37 to seg42 h'6 seg43 to seg48 h'7 seg49 to seg54 h'8 seg55 to seg60 h'9 seg61 to seg66 h'a seg67 to seg72 h'b seg73 to seg78 h'c seg79 to seg84 h'd seg85 to seg90 h'e seg91 to seg96 h'f note: seg72 to seg96 are driven by extension drivers.
hd66730/hd66731 76 ram data register (r9) this register (figure 16) stores 8-bit data that is written to or read from the ddram, cgram, or segram at the address indicated by the ram address counter (rac). the ram selection bit (rm1/0) selects the ram (ddram, cgram, segram). after the said ram is accessed, ram address is automatically incremented (decremented) by 1 according to the i/d bit. note that ram selection bits (rm1/0) and ram address register (r8) must be set before reading. if not, the first data read is invalid. if read instructions continue to be executed, however, data will be read correctly from the second read. test register (rf) this is a test register (figure 17) and must be set to h'00 at all times. this register is automatically cleared (h'00) by reset input; however, it must be cleared by software after power-on if the reset pin is not used. r/w 0/1 rs 1 db7 rd7 rd6 rd5 rd4 rd3 rd2 rd1 db0 rd0 figure 16 ram data register r/w 0 rs 1 db7 0000000 db0 0 figure 17 test register
hd66730/hd66731 77 table 18 instruction registers reg. index code execution clock no. (hex) register r/w rs db7 db6 db5 db4 db3 db2 db1 db0 description cycle ir index (idr) 0 0 id3 id2 id1 id0 designates the register number of the instruction register to access. id = 0000: r0 to 1001: r9 12 sr status (str) 1 0 bf nf1 nf0 lf3 lf2 lf1 lf0 indicates the busy flag (bf), display read line position (nf1/0), display read raster- row position(nl0 to nl3). 0 r0 0 entry mode (emr) 0 1 0 0 0 0 0 i/d rm1 rm0 designates ram address in crementation or decrementation (i/d) and ram selection (rm1/0). 12 r1 1 function set (fsr) 0 1 0 bst ext2 ext1 dt1 dt0 0 dcl clears display (dcl) and initializes the ddram address. selects duty drive ratio(dt1/0), enables extension driver (ext2/1) and sets the booster operation on. dcl = 1: 492 other: 12 r2 2 cursor control (ccr) 0 1 0 0 0 0 chm c cm1 cm0 designates cursor-on (c) and cursor display mode(cm1/0). executes cursor home (chm) instruction. 12 r3 3 display control 1 (dcr1) 0 1 0 0 0 0 0 st dc ds designates standby mode (st), character display on (dc), and segment display on (ds). 12 r4 4 display control 2 (dcr2) 0 1 0 0 nc1 nc0 0 0 nl1 nl0 sets the number of display characters(nc1/0) and display lines(nl1/0). 12 r5 5 scroll control 1 (scr1) 0 1 0 sn1 sn0 0 sl3 sl2 sl1 sl0 sets the display start line (sn1/0) and start raster-row (st0 to st3). 12 r6 6 scroll control 2 (scr2) 0 1 0 0 ps1 ps0 se4 se3 se2 se1 designates partial scroll columns (ps1/0) and scroll display line enable(se1 to se4). 12 r7 7 scroll control 3 (scr3) 0 1 0 0 sq5 sq4 sq3 sq2 sq1 sq0 sets the number of dots to be scrolled (sqr0 to sqr5). 12
hd66730/hd66731 78 table 18 instruction registers (cont) reg. index code execution clock no. (hex) register r/w rs db7 db6 db5 db4 db3 db2 db1 db0 description cycle r8 8 ram address (rar) 0 1 ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 resets the address address counter for ddram/cgram/ segram. ram is selected by rm1/0. 12 r9 9 ram data (rdr) 0/1 1 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 writes or reads data to and from ddram/cgram/ segram. ram is selected by rm1/0. 12 rf f test (tsr) 0 1 0 0 0 0 0 0 0 0 this is a test register. set 00 in this register. 12 note: the execution time depends on the input or oscillation frequency. bf = 1: internal processing being performed nf1/0: position of display read line lf0 to lf3: position of display read raster-row id= 1: address increment = 0: address decrement rm1/0: ram selection (00/01: ddram. (10: ggram, 11: segram) bst = 1: booster on ext2 = 1: common driver extension enable ext1 = 1: segment driver extension enable dt1/0: duty ratio (00: 1/14, 01: 1/27, 10: 1/40, 11: 1/53) dcl = 1: executes display-clear instruction chm = 1: executes cursor-home instruction c = 1: cursor on cm1/0: designates cursor mode (00: 12th raster-row, 01: blinking, 10: white/black inverse) st = 1: standby mode dc = 1: character display on ds = 1: segment display on nc1/0: sets the number of display characters (6 to 40 characters) nl1/0: sets the number of display lines (00: 1 line, 01: 2 lines, 11: 4 lines) sn1/0: designates the line to start displaying (00: first line, 01: second line, 10: third line, 11: fourth line) sl0 to sl3: designates scroll starting raster-row(0000: first raster-row, 1100: 13th raster-row) ps1/0: designates partial scroll (00: all columns scroll. 01: the leftmost column fixed, 10: the two leftmost columns fixed, 11: the three leftmost columns fixed) se1 to se4: designates which line to scroll (se = 1: enables the first line to be scrolled, etc.) sq0 to sq5: number of dots to scroll (0 to 48 dots) ra0 to ra7: ram address rd0 to rd7: ram data
hd66730/hd66731 79 reset function the hd66730/1 is reset by setting the reset pin to low level. during reset, the system performs next- control-register setting and executes instructions. the busy flag (bf) therefore indicates a busy state (bf = 1) at this time, which means that only the index register and status register can be accessed. display clear (ddram reset) is performed automatically by reset input. since more than 1,000 clocks of execution cycles are needed to initialize the ddram, the reset period must be set to more than this number. note that if the reset input conditions specified in electrical characteristics are not satisfied, the hd66730/1 will not operate correctly, and reset should be performed by software. initialization of instruction register function 1. index register: ir the index register cannot be initialized by reset. after reset release, the index register must be set to access a control register. 2. status register: sr bf = 1: busy state 3. entry mode register: r0 i/d = 1: +1 (incrementation) rm1/0 = 00: ddram selection 4. function set register: r1 bst = 0: booster off ext2/1 = 11: driver extension enable dt1/0 = 11: 1/53 duty drive dcl = 1: display-clear execution note: at least 1,000 clock cycles of execution time is needed to clear the ddram.
hd66730/hd66731 80 5. cursor control register: r2 chm = 1: cursor home execution c = 0: cursor display off cm1/0 = 00: 12th raster-row cursor display mode 6. display control register 1: r3 st = 0: standby mode clear dc = 0: character display off ds = 0: segment display off 7. display control register 2: r4 nc1/0 = 00: 6-column display mode nl1/0 = 00: 1-line display mode 8. scroll control register 1: r5 sn1/0 = 00: starts displaying from the first line. sl3 to sl0 = 0000: starts displaying from the first raster-row. 9. scroll control register 2: r6 ps1/0 = 00: partial scroll release se4 to se1 = 0000: disables dot scrolling for all lines. 10. scroll control register 3: r7 sq5 to sq0 = 000000: number of dots to be scrolled = 0 11. ram address register: r8 ram address register is automatically incremented during reset when display-clear is executed. note that after reset is released, this register must be reset by software before accessing ram.
hd66730/hd66731 81 initial setting of pin functions 1. bus/serial interface the input level of pin im selects the 8-bit bus or serial interface. for an 8-bit bus interface, data is written into the index register or read from the status register according to the level of pin r/w. note that pin rs must be held low during this time. for serial interface, data is written into the index register according to bit r/w. note that bit rs must be 0 during this time. during reset, only the index register and status register can be set and ram cannot be accessed. 2. lcd driver output since segment drivers (pins seg1 to seg71/119) are in a display-off state during reset, they output non-selective levels (v2/v3 level) during reset. at this time, a 4-line 6-character display alternates its current. common drivers (pins com1 to com24/53 and coms) output non-selective levels (v1/v4 level) during reset, and alternate its current for a 4-line 6-character display. note: pins com25/comd of hd66730 are grounded (0v) during reset. when pin com25 is used without expanding drivers to the common side, display may be performed using the liquid crystal drive voltage. in this case, adjust the liquid crystal voltage during reset. 3. extension driver interface output (hd66730) since bits ext2/1 are 11 during reset, extension is performed to both segment side and common side. pin cl2 outputs the oscillation (operation) frequency clock. pins cl1 and m output signals in a cycle corresponding to a 4-line 6-character display size. in addition, pins segd and com25/comd output low (ground level) since the display is turned off. 4. booster output the operation of the internal booster stops because bit bst becomes 0 during reset. note: the potential of pins v5out2 and v5out3 increases by about +0.7 v with respect to gnd level when the booster stops. when using external polarized capacitors, make sure that no reverse bias occurs.
hd66730/hd66731 82 interfacing to the mpu the hd66730/1 enters 8-bit bus interface mode when the im pin is set high. the hd66730/1 can interface with the mpu via an i/o port. use the serial interface when there are restraints in the bus wiring width. instruction is executed when data is written into the control register. in this case, only the status register can be read (busy check, etc.). in this case, check the busy flag when accessing (polling), or insert an interval considering the execution time and perform the next access when the internal process has completely finished. the instruction execution time depends on the hd66730/1 operation frequency. when using the internal oscillation circuit of the hd66730/1, the instruction time will change as the oscillation frequency does. figure 18 shows an example of an 8-bit data transfer timing sequence. figure 19 shows an example of interface between hd66730/1 and 8-bit microcomputers.
r/w e internal signal db7 db6 to db0 internal operation (busy) data busy busy not busy data control register write busy flag check busy flag check busy flag check index register write rs figure 18 example of an 8-bit data transfer timing sequence c0 c1 c2 a0 to a7 e rs r/w db0 to db7 8 h8/325 i/o port interface hd66730 hd66731 figure 19 example of interfacing with 8-bit microcomputers
hd66730/hd66731 83 transferring serial data the hd66730/1 enters serial interface mode when the im pin is set low. a three-line clock-synchronous transfer method is used. the hd66730/1 receives serial input data (sid) and transmits serial output data (sod) by synchronizing with a transfer clock (sclk) sent from the master side. when the hd66730/1 interfaces with several chips, chip select pin (cs*) must be used. the transfer clock (sclk) input is activated by making chip select (cs*) low. in addition, the transfer counter of the hd66730/1 can be reset and serial transfer synchronized by making chip select (cs*) high. here, since the data which was being sent at reset is cleared, restart the transfer from the first bit of this data. in a minimum system where a single hd66730/1 interfaces to a single mpu, an interface can be constructed from the transfer clock (sclk) and serial input data (sid). in this case, chip select (cs*) should be fixed to low. the transfer clock (sclk) is independent of operational clock (clk) of the hd66730/1. however, when several instructions are continuously transferred, the instruction execution time determined by the operational clock (clk) (see continuous transfer) must be considered since the hd66730/1 does not have an internal transmit/receive buffer. figure 20 shows the basic procedure for transferring serial data. to begin with, transfer the start byte. by receiving five consecutive bits of 1 (synchronizing bit string) at the beginning of the start byte, the transfer counter of the hd66730/1 is reset and serial transfer is synchronized. the 2 bits following the synchronizing bit string (5 bits) specify transfer direction (r/ w bit) and register select (rs bit). be sure to transfer 0 in the 8th bit. after receiving the start byte, instructions are received and the data/busy flag is transmitted. when the transfer direction and register select remain the same, data can be continuously transmitted or received. the transfer protocol is described in detail in the following.
hd66730/hd66731 84 12345678910111213141516 123456789101112131415161718192021222324 11111r/wrs0d0d1d2d30000d4d5d6d70000 start byte instruction a) serial data input (receiving) cs * (input) sclk (input) sid (input) cs * (input) sclk (input) sid (input) sod (output) synchronizing bit string lower data upper data 1st byte 2nd byte b) serial data output (transmitting) synchronizing bit string lower data upper data start byte status/data read 11111r/wrs 000000000 d0 d1 d2 d3 d4 d5 d6 d7 figure 20 basic procedure for transferring serial data
hd66730/hd66731 85 receiving (write) after receiving the start synchronizing bit string, the r/w bit (= 0), and the rs bit in the start byte, an 8-bit instruction is received in 2 bytes: the lower 4 bits of the instruction are placed in the lsb of the first byte, and the higher 4 bits of the instruction are placed in the lsb of the second byte. be sure to transfer 0 in the following 4 bits of each byte. when instructions are received with r/w bit and rs bit unchanged, continuous transfer is possible (see continuous transfer in the following). transmitting (read) after receiving the synchronizing bit string, the r/w bit (= 0), and the rs bit in the start byte, 8-bit read data is transmitted from pin sod in the same way as receiving. when read data is transmitted with r/w bit and rs bit unchanged, continuous transfer is possible (see continuous transfer in the following). the status register (sr) is read when the rs bit is 0. ram data is read out when the rs bit is set to 1 after designating ram data register (r9) with the index register (ir). bits rm1/0 of entry mode register (r0) select the ram. when reading ram data, an interval longer than the ram reading time must be taken after the start byte has been accepted and before the first data has been read out. during transmission (data output), the sid input is continuously monitored for a start synchronizing bit string (11111). once this has been detected, the r/ w and rs bits are received. accordingly, 0 must always be input to sid when transmitting data continuously. continuous transfer when instructions are received with the r/w bit and rs bit unchanged, continuous receive is possible without inserting a start byte between instructions. after receiving the last bit (the 8th bit in the 2nd byte) of an instruction, the system begins to execute it. to execute the next instruction, the instruction execution time of the hd66730/1 must be considered. if the last bit (the 8th bit in the 2nd byte) of the next instruction is received during execution of the previous instruction, the instruction will be ignored. in addition, if the next unit of data is read before read execution of previous data is completed for ram data, normal data is not sent. to transfer data normally, the busy flag must be checked. however, if the amount of wiring used for transmission needs to be reduced, or if the burden of polling on the cpu needs to be lightened, transfer can be performed without reading the busy flag. in this case, insert a transfer wait between instructions so that the current instruction has time to complete execution. figure 21 shows the procedure for continuous data transfer.
hd66730/hd66731 86 start byte instruction (1) 1st byte 2nd byte instruction (2) 1st byte 2nd byte start byte start byte instruction (1) 1st byte 2nd byte instruction (3) 1st byte 2nd byte instruction (2) 1st byte 2nd byte start byte busy read instruction (1) execution time instruction waiting time (not busy state) instruction (1) execution time instruction (2) execution time instruction (3) execution time wait wait wait wait start byte data read (1) data read (2) ram data read time (1) ram data read time (2) sclk (input) sid (input) sod (output) sclk (input) sid (input) sclk (input) sid (input) sod (output) i) continuous data write by polling processing ii) continuous data write by cpu wait insert iii) continuous data write by cpu wait insert ram data read time (3) wait figure 21 procedure for continuous data transfer
hd66730/hd66731 87 combined display of full-size and half-size characters the hd66730/1 performs display from the left edge of the display combining 12-dot full-size (character size: 11 12 dots) and 6-dot half-size characters (character size: 6 12 dots). there will be a one-dot space between these fonts. the most significant bit in the data (8 bits) in ddram is allocated to the designation bit indicating a full- size or half-size character. when this msb is 0, the full-size character is selected, and when 1, the half-size character is selected. when the full-size character is selected, 2 bytes of ddram are linked and used as a 16-bit code (figure 22). in this case, the lower byte is written into the smaller ddram address. 12 bits of this 16-bit code are used as character codes. up to 4096 character codes can be specified. in addition, two of the remaining four bits can be allocated to a display-attribute code and can designate white/black inverted display for individual characters (refer to display attribute designation). table 18 shows the relationship between the 16-bit designated jis code and the hd66730/1 12-bit character code. 8-bit data designating half-size characters are used as an 8-bit code (figure 23). specifically, 7 bits of the 8-bit half-size characters become the character codes, so that a total of 128 characters can be displayed (alphanumeric characters and symbols can be displayed as half-size characters). user fonts can be displayed using the cgram. special symbols not included in the internal cgrom or the jis level-2 kanji set can be displayed as needed. since the display font size of the cgram is 12 13 dots, cgram fonts can be displayed to the right, left, top or bottom, in order to be used to display double- size characters or graphics. note that the display-attribute code (a1/a0) designation that is to be written into the ddram is ignored when the cgram is used. in this case, bits 6 and 7 in the cgram are used for display-attribute-code designation. refer to cgram for details. table 19 relationship between jis codes and hd66730 character codes jis first byte code: b1 to b7 (7 bits) jis second byte code: a1 to a7 (7 bits) cgram address for user fonts: u0 to u2 (3 bits) character code arrangement of hd66730 jis b7 b6 b5 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 non-kanji 010a7a6b3b2b100a5a4a3a2a1 level 1 kanji 011b7b4b3b2b1a7a6a5a4a3a2a1 level 1 kanji 100b7b4b3b2b1a7a6a5a4a3a2a1 user font ? 00000000u2u1u0 upper byte lower byte
hd66730/hd66731 88 full-size character format lower character code 0 upper character code display attribute code upper byte lower byte display attribute code: a1/a0 (2 bits) character code: c11 to c0 (12 bits) msb lsb a1 a0 0 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 figure 22 full-size character codes half-size character format character code character code: c6 to c0 (7 bits) msb lsb 1 c6 c5 c4 c3 c2 c1 c0 figure 23 half-size character codes
hd66730/hd66731 89 an example of displaying full-size and half-size characters together is described here. full-size character display conforms to jis (16 bits). perform code conversion (16 bits ? 12 bits) according to the relationship between the 16-bit jis code and the hd66730/1 12-bit character code and write two-byte character data to the ddram (write the lower byte to the smaller ddram address). the example is shown in table 19. when displaying a half-size character, refer to table 5 the hd66730/1 half- size font list and write one-byte character data into the ddram. the example is shown in table 20. figure 24 shows how to set data to the ddram when performing a 2-line display and figure 25 shows the resulting liquid crystal display. table 20 example of full-size font conversion displayed character jis code (first/second byte) character code (c11 to c0) 45/6c (hex) aec (hex) 35/7e (hex) 2fe (hex) 45/54 (hex) ad4 (hex) 3e/2e (hex) 72e (hex) 4a/3f (hex) d3f (hex) 3b/54 (hex) 5d4 (hex) 4b/5c (hex) ddc (hex) 44/2e (hex) a2c (hex) 24/4e (hex) a0e (hex) table 21 example of half-size font code display character character code (c0 to c11) 1 31 (hex) 2 32 (hex) 0 30 (hex) , 2c (hex) m 4d (hex) c 43 (hex)
hd66730/hd66731 90 0 000 1010 1110 1100 0 000 0010 1111 1110 0 000 1010 1101 0100 0 000 0111 0010 1110 0 000 1101 0011 1111 0 000 0101 1101 0100 0 000 1101 1101 1100 0 000 1010 0010 1110 1 011 0001 0 000 1010 0000 1110 1 011 0010 1 011 0000 1 010 1100 1 100 1101 1 100 0011 00 (hex) 01 (hex) 02 (hex) 03 (hex) 04 (hex) 05 (hex) 06 (hex) 07 (hex) 08 (hex) 09 (hex) 0a (hex) 0b (hex) 1st-line data 40 (hex) 41 (hex) 42 (hex) 43 (hex) 44 (hex) 45 (hex) 46 (hex) 47 (hex) 48 (hex) 49 (hex) 4a (hex) 4b (hex) address address 2nd-line data 0 : full-size designation 1 : half-size designation , figure 24 example of ddram character code (2-line display mode) figure 25 example of liquid crystal display
hd66730/hd66731 91 display attribute designation the hd66730/1 allocates 12 bits of the full-size 16-bit code character to an abbreviated character code and 2 bits to a display-attribute code (figure 26). white/black inverted display, blinking display, and white/black inverted blinking display can be designated for each full-size character (table 21). display attribute control is performed for a 12 13 dot matrix unit that includes a 11 12 dot full-size character and a column of dots to the right and a row of dots to the bottom (figure 27). the blinking cycle for blinking display and white/black inverted blinking display is 64 frames. blinking display is performed by changing the display pattern every 32 frames. since the 8-bit code designated for half-size characters cannot accommodate a display attribute, they will always be displayed normally. table 22 display attribute designation a1 a0 display state 0 0 normal display 0 1 white/black inverted display 1 0 blinking display 1 1 white/black inverted blinking display upper character code 0 a1 a0 0 c11 c10 c9 c8 attribute code lower character code c7 c6 c5 c4 c3 c2 c1 c0 figure 26 full-size code format
hd66730/hd66731 92 0 00 0 1010 1110 1100 ddram code normal display 0 01 0 1010 1110 1100 ddram code white/black inverted display 0 10 0 1010 1110 1100 ddram code blink display 0 11 0 1010 1110 1100 ddram code white/black inverted blinking display a) example of normal display b) example of white/black inverted display c) example of blinking display d) example of white/black inverted blinking display alternates display by 32 frames alternates display by 32 frames figure 27 setting codes in the ddram and display examples
hd66730/hd66731 93 horizontal smooth scroll data shown on the display can be scrolled horizontally to the left for a specified number of dots (figure 28). the number of dots are set in scroll control register 3 (scr3: r7), and the display lines to be scrolled are designated by the display line enable bits (se1/se2/se3/se4) in scroll control register 2 (scr2: r6). because the number of dots that can be set for scrolling here is 48, scrolling for more than this number can be achieved by shifting to the left by four characters of character code data in ddram for the scroll display line in question, rewriting the characters, and then scrolling again. when rewriting ddram while displaying characters, however, character output will momentarily breakdown, and the display may flicker. in this case, first check which display lines are currently being displayed by referring to nf1/0 (line 1 to the line 4) and display raster-rows lf0 to lf3 (raster-row 1 to raster-row 13) in the status register, and then rewrite a ddram line that is not being displayed. keep in mind that scroll display line enable bits (se1 to se4) can be used to designate those display lines for which horizontal smooth scroll is desired. in partial scroll, one to three leftmost characters on the display as specified by the partial scroll bits (ps1/0) of the scroll control register 2 (scr: r6) are fixed and the remaining characters undergo a smooth scroll to perform partial smooth scroll. when performing horizontal smooth scroll, the number of characters to be displayed (nc1/0: r4) must be at least 4 characters more than the number of characters actually displayed on the liquid crystal display. for example, set 10 or more display characters (nc1/0) for a single-chip 6-character display.
hd66730/hd66731 94 performs no shift ? scr3 = ?0?(hex) shifts to the left by one dot ? scr3 = ?1?(hex) shifts to the left by two dots ? scr3 = ?2?(hex) shifts to the left by ten dots ? scr3 = ?a?(hex) shifts to the left by 48 dots ? scr3 = ?0?(hex) figure 28 example of horizontal smooth scroll display
hd66730/hd66731 95 examples of register setting db7 db6 db5 db4 db3 db2 db1 db0 r/w rs 00 00 00 1 1 01 00 01 shifts the second line to the left by one dot 01 10 shifts the second line to the left by two dots 01 10 shifts the second line to the left by three dots cpu wait cpu wait cpu wait 4 5 6 0 0 0 0 10 0 0 0 0 11 0 0 0 0 01 00 01 2 10 0 0 index register set (r6 designation) enables scroll (scrolls only the second line) 01 10 11 shifts the second line to the left by 48 dots * 51 00 0 0 10 00 00 00 01 3 index register set (r7 designation) 11 0 note: the number of dots that can be specified for scrolling is 48. scrolling for more than this number can be achieved by rewriting ddram data and scrolling again from dot 0. note that the number of characters shown on the lcd and the number of scroll characters must be less than the number of maximum display characters (1-line display mode: 40 characters, 2-line display mode: 20 characters, 4-line display mode: 10 characters). figure 29 example of executing smooth scroll to the left
hd66730/hd66731 96 0110 00 shifts the second line to the left by 48 dots * 0 1 1 0 shifts the second line to the left by 47 dots cpu wait cpu wait 4 5 0111 0 shifts the second line to the left by one dot 49 0 0 1 1 11 1 1 0 1 001 0 0 0110 00 perform no shift cpu wait 51 00 0 0 db7 db6 db5 db4 db3 db2 db1 db0 r/w rs 000000 01 1 010001 2 10 0 0 index register set (r6 designation) enables scroll (scrolls only the second line) 10 000000 01 3 index register set (r7 designation) 11 note: the number of dots that can be specified for scrolling is 48. rewrite 48 dots (4 characters) of data inside the ddram and shift them to the right before scrolling. scrolling for more than this number can be achieved by rewriting the data of ddram and begin scrolling from dot 48 again. note that the number of characters shown on the lcd and the number of scroll characters must be less than the number of maximum display characters (1-line display mode: 40 characters, 2-line display mode: 20 characters, 4-line display mode: 10 characters). figure 30 example of executing smooth scroll to the right
hd66730/hd66731 97 partial smooth scroll partial smooth scroll displays one to three leftmost characters as fixed while the remaining ones undergo a horizontal smooth scroll in the left and right direction. specifically, the number of leftmost characters to be fixed is specified by the partial scroll bits (ps1/0) in the scroll control register 2 (scr2: r6). for example, when bits ps1/0 are 10, the two leftmost characters are fixed; when 11, the three leftmost characters are fixed. although half-size characters can be displayed in a fixed display area, they must be displayed in even- numbered groups of two, four or six characters. figure 31 shows an example of smooth scroll performed in a display when bits ps1/0 are set to 10. the two leftmost characters ( ) are displayed as fixed, and the remaining four characters undergo a smooth scroll. perform no shift ? ps1/0 = ?0 ? scr3 = ?0?(hex) shifts to the left by one dot ? ps1/0 = ?0 ? scr3 = ?1?(hex) shifts to the left by two dots ? ps1/0 = ?0 ? scr3 = ?2?(hex) shifts to the left by three dots ? ps1/0 = ?0 ? scr3 = ?3?(hex) shifts to the left by 16 dots ? ps1/0 = ?0 ? scr3 = ?a?(hex) shifts to the left by 32 dots ? ps1/0 = ?0 ? scr3 = ?0?(hex) figure 31 example of partial smooth scroll display
hd66730/hd66731 98 vertical smooth scroll vertical smooth scroll up and down can be performed by setting the number of display lines (nl1/0: r4) to a value greater than the actual number of liquid crystal display lines, which can be set by the duty drive ratio (dt1/0: r1) to 1/14 (1-line display), 1/27 (2-line display), 1/40 (3-line display), or 1/53 (4-line display). the display line setting (nl1/0: r4), which controls the display, can select 1-line display mode, 2-line display mode, or 4-line display mode. for example, to perform normal vertical smooth scroll for a 3-line liquid crystal display with a duty ratio of 1/40, set the number of display lines (nl1/0: r4) to 4 lines. note that if vertical smooth scroll is performed when the number of actual liquid display lines is the same as the number of set display lines, the display line that has scrolled out of the display will appear again from the bottom (or the top) (this function is called lap-around). in a 4-line crystal liquid display, only the lap-around function can be performed. vertical smooth scroll is controlled by incrementing or decrementing the display line (sn1/0), which indicates which line to start from, and the display raster-row (sl0 to sl3). for example, when performing smooth scroll up, the display raster-row (sl0 to sl3) is incremented from 0000 to 1100 in order to scroll 12 raster-rows. moreover, by incrementing the display line (sn1/0) and then incrementing the display raster-row from 0000 to 1100 again, a total of 25 raster-rows can be scrolled. since the ddram is only 80 bytes, its data must be rewritten when performing continuous scroll exceeding this capacity.
hd66730/hd66731 99 performs no scroll ? sn1/0 = ?0 ? sl3 to 0 = ?000 1-line scroll ? sn1/0 = ?0 ? sl3 to 0 = ?001 2-line scroll ? sn1/0 = ?0 ? sl3 to 0 = ?010 7-line scroll ? sn1/0 = ?0 ? sl3 to 0 = ?111 12-line scroll ? sn1/0 = ?0 ? sl3 to 0 = ?100 figure 32 example of vertical smooth scroll display
hd66730/hd66731 100 examples of register setting (2-line liquid crystal drive: dt1/0 = 01, 4-line display mode: nl1/0 = 11) db7 db6 db5 db4 db3 db2 db1 db0 r/w rs 000000 1 1 index register set (r5 designation) 01 0 010 001 scrolls one raster-row up (begins display from the second raster-row of the first line) 2 0 0 0 0 cpu wait 010 010 scrolls two raster-rows up (begins display from the third raster-row of the first line) 3 0 0 0 0 cpu wait 010 011 scrolls three raster-rows up (begins display from the fourth raster-row of the first line) 4 0 0 0 0 cpu wait 010 000 scrolls 12 raster-rows up (begins display from the 13th raster-row of the first line) 13 1 1 0 0 cpu wait 010 000 scrolls 13 raster-rows up (begins display from the first raster-row of the second line and displays the second and third lines) 14 0 0 0 1 cpu wait 010 000 scrolls 25 raster-rows up (begins display from the 13th raster-row of the second line) 26 1 1 0 1 cpu wait 010 100 scrolls 26 raster-rows up (begins display from the first raster-row of the third line and displays the third and fourth lines) 27 0 0 0 0 cpu wait note: the ddram has 80 bytes. for a 4-line display mode, a 4-line 10-character/line display can therefore be performed. although the line and raster-row for scrolling can be designated as desired, the first raster-row of the first line will be displayed after displaying raster-row 13 of line 4. figure 33 example of performing smooth scroll up
hd66730/hd66731 101 db7 db6 db5 db4 db3 db2 db1 db0 r/w rs 00 0000 1 1 index register set (r5 designation) 01 0 01 0 100 scrolls one raster-row down (begins display from the 13th raster-row of the fourth line) 2 1 1 0 1 cpu wait 01 0 111 scrolls two raster-rows down (begins display from the 12th raster-row of the fourth line) 3 0 1 0 1 cpu wait 01 0 110 scrolls three raster-rows down (begins display from the 11th raster-row of the fourth line) 4 0 1 0 1 cpu wait 01 0 100 scrolls 13 raster-rows down (begins display from the first raster-row of the fourth line) 14 0 0 0 1 cpu wait 01 0 100 scrolls 14 raster-rows down (begins display from the third raster-row of the 13th line) 15 1 1 0 0 cpu wait 01 0 100 scrolls 26 raster-rows down (begins display from the third raster-row of the first line) 27 0 0 0 0 note: the ddram has 80 bytes. for a 4-line display mode, a 4-line 10-character/line display can therefore be performed. although the line and raster-row for scrolling can be designated as desired, the first raster-row of the first line will be displayed after displaying raster-row 13 of line 4. figure 34 example of performing smooth scroll down
hd66730/hd66731 102 extension driver lsi interface (hd66730) the hd66730 can interface with extension drivers using extension driver interface signals cl1, cl2, d, and m output from the hd66730, increasing the number of display characters (figure 35). although the liquid crystal driver voltage that drives the booster of the hd66730 can also be used as the driver power supply of extension drivers, the output voltage drop of the booster increases as the load of the booster increases. com1 to com25 seg1 to seg72 seg1 to seg71 hd66730 2-line/6-character display a) single-chip operation com1 to com25 cl1 d cl1 cl2 m hd66730 seg1 to seg71 hd66002 y1 to y73 2-line/12-character display b) using extension driver cl2 d m figure 35 hd66730 and extension driver lsi connection
hd66730/hd66731 103 interfacing with the liquid crystal panel by connecting the hd66730 to extension drivers, the display can be expanded up to a 1-line/40-character, 2-line/20-character, or a 4-line/10-character display configuration. bits dt1/0 set the duty drive ratio and bits nc1/0 set the number of characters per line. in addition, bits nl1/0 sets the number of display lines during display read control. table 22 shows the relationship between the number of characters actually displayed on the liquid crystal panel and the corresponding number of extension drivers needed. table 23 relationship between the number of liquid crystal display characters and extension drivers number of display characters per line display lines 6 characters 10 characters 12 characters 16 characters 20 characters 40 characters duty drive 1 line (0/0) (2/0) (2/0) (3/0) (5/0) (11/0) 1/14 2 lines (0/0) (2/0) (2/0) (3/0) (5/0) display disabled 1/27 3 lines (0/1) (2/1) display disabled display disabled display disabled display disabled 1/40 4 lines (0/1) (2/1) display disabled display disabled display disabled display disabled 1/53 notes: 1. numbers in parentheses = (number of extension segment drivers/number of common drivers) 2. this is an example when using the 40 output extension drivers, and when nh represents display characters and nd extension driver outputs, the number of extension drivers needed can generally be calculated as follows: [number of extension drivers] = (12 * nh ?71 ?1)/nd] - 3. the right-edge segment (space between characters) is not displayed in 6-character or 16- character display. 4. horizontal smooth scroll cannot be performed during an 1-line/40-character, 2-line/20-character, 3-line/10-character, or 4-line/10-character display.
hd66730/hd66731 104 example of interfacing with a 1-line display panel com1 com2 seg1 seg2 seg71 coms hd66730 16 com12 seg12 + - ? = 1 note: the rightmost dot-column space of the 6th character cannot be displayd. figure 36 example of 1-line/6-character + 71-segment display (using 1/14 duty) 16712 com1 com2 seg1 seg2 seg71 coms hd66730 com12 seg12 com14 com15 com25 + - ? = 1 note: 1. the above figure shows how a liquid crystal panel can be arranged into a 1-line/12-character display while operating the hd66730 in 2-line/6-character display mode. although the duty ratio becomes high, extension drivers will not be needed. co m13 for spaces between displa y lines will not be needed. figure 37 example of 1-line/12-character + 71-segment display (using 1/27 duty)
hd66730/hd66731 105 example of interfacing with a 2-line display panel 16 com1 com2 com14 seg1 com13 hd66730 com12 seg2 com25 coms seg12 seg71 + - ? = 1 note: 1. when performing vertical smooth scroll, or displaying double-size characters or graphic figures by the cgram, com13 can be used for spaces between lines. display can be performed continuously vertically. figure 38 example of 2-line/6-character + 71-segment display (using 1/27 duty)
hd66730/hd66731 106 coms com1 com2 com19 seg1 seg2 seg12 seg72 com20 com39 com40 hd66731 16 note: coms and com40 output the same. + = + = figure 39 example of 3-line/6-character + 72-segment display (using 1/40 duty)
hd66730/hd66731 107 interfacing between hd66730 and hd66002 mpu rs r/w e db4~db7 db0~db3 hd66730 osc1 osc2 rf v1 v2 v3 v4 v5 v cc gnd 26 cl1 cl2 m d rs r/w e db4~db7 db0~db3 com1 ~com25 coms com1 com2 com3 seg1 seg2 seg3 seg226 seg227 seg228 com24 com25 71 seg1 ~seg71 v ee (?v) r gnd (0v) v cc (+3v) r 2 r r r 19-character 2line lcd panel (228 25 dot + 96 segments) 1/27 duty 80 y80, y79,?2, y1 hd66002 (1) v cc shl e d1r v1 v3 v4 v2 cl1 cl2 m d2r, d3l test1 test2 fcs gnd v cc v ee car d0l open 77 y80, y79,?2, y1 hd66002 (2) v cc shl e d1r v1 v3 v4 v2 cl1 cl2 m d2r, d3l test1 test2 fcs gnd v cc v ee car d0l open open input waveform timechart cl2 d cl1 (shift clock) 1 seg.240 2 3 4 238 239 240 (latch clock) seg.239 seg.238 seg.237 seg.3 seg.2 seg.1 notes: 1. the resistance of r depends on the type of the lcd panel used (usually 2 k to 10 k ). 2. to stabilize the power supply, place two 0.1- f capacitors near each lcd driver: one between the v cc and gnd pins, and the other between the v cc and v ee . v1 v2 v5 v4 v3 figure 40 example of display extension curcuit
hd66730/hd66731 108 oscillator figure 41 shows the optimal value of the oscillation frequency or the external clock frequency depends on the duty drive ratio setting (dt1/0), number of display lines (nl1/0), and the number of display characters (nc1/0) in the hd66730/1. the oscillation frequency or the external clock frequency must be adjusted according to the frame frequency of the liquid crystal drive. 1) when an external clock is used 2) when an internal oscillator is used osc1 osc1 osc2 clock rf hd66730 hd66731 hd66730 hd66731 note: the oscillator frequency can be adjusted by an oscillator resistor (rf). refer to electrical characteristics for the relationship between the oscillator resistor (rf) and the oscillator frequency. if rf is increased or power supply voltage is decreased, the oscillator frequency decreases. figure 41 oscillator connections
hd66730/hd66731 109 relationship between the oscillation frequency and the liquid crystal display frame frequency figures 42 to 45 and tables 24 to 27 show the oscillation frequency and the external clock frequency for various registor settings when the frame frequency is 80 hz. 1 2 3 4 13 14 1 2 3 13 14 1-line selection period v cc v1 com1 1 frame 1 frame (number of dots per screen) (number of dots per screen) v4 v5 figure 42 frame frequency (1/14 duty cycle)
hd66730/hd66731 110 table 24 1/14 duty drive number of display lines: 1-line display (nl1/0 set value): (00) number of display characters 6 characters 20 characters 40 characters (nc1/0 set value) (00) (01) (11) 1-line selection period (dot) 72 dots 240 dots 480 dots number of dots per screen (dot) 1008 dots 3360 dots 6720 dots oscillation frequency (khz)* 70 235 475 number of display lines: 2-line display (nl1/0 set value): (01) number of display characters 6 characters 20 characters 40 characters (nc1/0 set value) (00) (01) (11) 1-line selection period (dot) 72 dots 120 dots 240 dots number of dots per screen (dot) 1008 dots 1680 dots 3360 dots oscillation frequency (khz)* 70 120 235 number of display lines: 4-line display (nl1/0 set value): (11) number of display characters 6 characters 10 characters (nc1/0 set value) (00) (01) 1-line selection period (dot) 72 dots 120 dots number of dots per screen (dot) 1008 dots 1680 dots oscillation frequency (khz)* 70 120 note: * the frequencies in table 23 are examples when the frame frequency is set to 70 hz. adjust the oscillation frequency so that a optimum frame frequency can be obtained.
hd66730/hd66731 111 1/27 duty cycle (dt1/0 = 01: 2-line drive) 1 2 3 4 26 27 1 2 3 26 27 1-line selection period v cc v1 com1 1 frame 1 frame (number of dots per screen) (number of dots per screen) v4 v5 figure 43 frame frequency (1/27 duty cycle) table 25 1/27 duty drive number of display lines: 2-line display (nl1/0 set value): (01) number of display characters 6 characters 10 characters 20 characters (nc1/0 set value) (00) (01) (11) 1-line selection period (dot) 72 dots 120 dots 240 dots number of dots per screen (dot) 1944 dots 3240 dots 6480 dots oscillation frequency (khz)* 135 225 475 number of display lines: 4-line display (nl1/0 set value): (11) number of display characters 6 characters 10 characters (nc1/0 set value) (00) (01) 1-line selection period (dot) 72 dots 120 dots number of dots per screen (dot) 1944 dots 3240 dots oscillation frequency (khz)* 135 225 note: * the frequencies in table 24 are examples when the frame frequency is set to 70 hz. adjust the oscillation frequency so that an optimum frame frequency can be obtained.
hd66730/hd66731 112 1/40 duty cycle (dt1/0 = 10: 3-line drive) 1 2 3 4 39 40 1 2 3 39 40 1-line selection period v cc v1 com1 1 frame 1 frame ( number of dots per screen ) (number of dots per screen) v4 v5 figure 44 frame frequency (1/40 duty cycle) table 26 1/40 duty drive number of display lines: 4-line display (nl1/0 set value): (11) number of display characters 6 characters 10 characters (nc1/0 set value) (00) (01) 1-line selection period (dot) 72 dots 120 dots number of dots per screen (dot) 2880 dots 4800 dots oscillation frequency (khz)* 200 335 note: * the frequencies in table 25 are examples when the frame frequency is set to 70 hz. adjust the oscillation frequency so that an optimum frame frequency can be obtained.
hd66730/hd66731 113 1/53 duty cycle (dt1/0 = 11: 4-line drive) 1 2 3 4 52 53 1 2 3 52 53 1-line selection period v cc v1 com1 1 frame 1 frame (number of dots per screen) (number of dots per screen) v4 v5 figure 45 frame frequency (1/53 duty cycle) table 27 1/53 duty drive number of display lines: 4-line display (11) (nl1/0 setting value): (00) (01) number of display characters 6 characters 10 characters (nc1/0 setting value) (00) (01) 1-line selection period (dot) 72 dots 120 dots number of dots per screen (dot) 3816 dots 6360 dots oscillation frequency (khz)* 265 445 note: * the frequencies in table 26 are examples when the frame frequency is to 80 hz. adjust the oscillation frequency so that an optimum frame frequency can be obtained.
hd66730/hd66731 114 power supply for liquid crystal display drive the hd66730/1 incorporates a booster for raising the lcd voltage two or three times that of the reference voltage input below v cc (figure 48). a two or three times boosted voltage can be obtained by externally attaching two or three 1- m f capacitors. if the lcd panel is large and needs a large amount of drive current, the values of bleeder resistors that generate the v1 to v5 potential are made smaller. however, the load current in the booster and the voltage drop increases in this case. we recommend setting the resistance value of each bleeder larger than 4.7 k w and to hold down the dc load current to 0.4 ma if using a booster circuit. an external power supply should supply lcd voltage if the dc load current exceeds 0.7 ma (figure 49). refer to electrical characteristics showing the relationship between the load current and booster voltage output. table 27 shows the duty factor and bleeder resistor value for power supply for liquid crystal display drive. table 28 duty factor and bleeder resistor value for power supply for liquid crystal display drive item data drive lines (dt1/0 setting value) 1 2 3 4 duty factor 1/14 1/27 1/40 1/53 bias 1/4.7 1/6.2 1/7.3 1/8.3 bleeder resistance value r1 r r r r r0 r*0.7 r*2.2 r*3.3 r*4.3 note: * r changes depending on the size of a liquid crystal panel. normally, r must be 4.7 k w to 20 k w . adjust r to the optimum value with the consumption current and display picture quality. v cc v1 v2 v3 v4 v5 v cc r1 r1 r0 r1 r1 vr v ee figure 46 example of power supply for liquid crystal display drive (with external power supply)
hd66730/hd66731 115 v cc v1 v2 v3 v4 v5 v cc c1 c2 vci gnd v5out2 r1 r1 r0 r1 r1 c1 c2 vci gnd v5out2 r1 r1 r0 r1 r1 v5out3 v5out3 + + + + 1 f + 1 f gnd gnd 1 f 1 f 1 f gnd gnd (double boosting) (triple boosting) v cc v1 v2 v3 v4 v5 v cc thermistor thermistor notes: 1. 2. 3. 4. 5. 6. the reference voltage input (vci) must be set below the power supply (v cc ). current that flows into reference voltage input (vci) is 2-3 times larger than the load current flowing through bleeder resistors. note that a reference voltage drop occurs due to the current flowing into the vci input when a reference voltage (vci) is generated by resistor division. the amount of output voltage (v5out2/v5out3) drop of a booster circuit also increases as the load current flowing through bleeder resistors increases. thus, set the bleeder resistance as large as possible (4.7 k w or greater) without affecting display picture quality. adjust the reference voltage input (vci) according to the fluctuation of booster characteristics because the output voltage (v5out2/v5out3) drop depends on the load current, operation temperature, operation frequency, capacitance of external capacitors, and manufacturing tolerance. refer to electrical characteristics for details. adjust the reference voltage input (vci) so that the output voltage (v5out2/v5out3) after boosting will not exceed the absolute maximum rating of liquid crystal power supply voltage (15v). make sure that you connect polarized capacitors correctly. figure 47 example of power supply for liquid crystal display drive (with internal booster)
hd66730/hd66731 116 v cc v1 v2 v3 v4 v5 c1 c2 v ci gnd v5out2 1 f 1 f ?r1= 4.7k to 15k i) example of normal power supply r1 r1 r0 r1 r1 1 f v5out3 + + + v cc gnd gnd v cc v1 v2 v3 v4 v5 c1 c2 v ci gnd v5out2 1 f 1 f ?r1= 15k to 47k ?c0= 0.1 f to 0.5 f ii) example of low power supply r1 c0 r1 r0 r1 r1 1 f v5out3 + + + v cc gnd gnd + + + + figure 48 example of power supply for low power consumption v cc v1 v2 v3 v4 v5 c1 c2 v ci gnd v5out2 1 f r1 r1 r0 r1 r1 1 f v5out3 + + v cc rth gnd 1 f + gnd gnd v cc v1 v2 v3 v4 v5 c1 c2 v ci gnd v5out2 1 f r1 r1 r0 r1 r1 1 f v5out3 + + v cc rth gnd 1 f + gnd gnd v cc v1 v2 v3 v4 v5 c1 c2 v ci gnd v5out2 1 f r1 r1 r0 r1 r1 rb 1 f v5out3 + + v cc rth ra gnd 1 f + gnd gnd figure 49 example of temperature compensation circuit
hd66730/hd66731 117 absolute maximum ratings (hd66730)* item symbol value unit notes power supply voltage (1) v cc ?.3 to +7.0 v 1 power supply voltage (2) v cc ?5 ?.3 to +17.0 v 1, 2 input voltage vt ?.3 to v cc + 0.3 v 1 operating temperature t opr ?0 to +75 c storage temperature t stg ?5 to +125 c4 note: * if the lsi is used above these absolute maximum ratings, it may become permanently damaged. using the lsi within the following electrical characteristic limits is strongly recommended for normal operation. if these electrical characteristic conditions are also exceeded, the lsi will malfunction and cause poor reliability. absolute maximum ratings (hd66731)* item symbol value unit notes power supply voltage (1) v cc ?.3 to +7.0 v 1 power supply voltage (2) v cc ?5 ?.3 to +17.0 v 1, 2 input voltage vt ?.3 to v cc + 0.3 v 1 operating temperature t opr ?0 to +85 c storage temperature t stg ?5 to +110 c4 note: * if the lsi is used above these absolute maximum ratings, it may become permanently damaged. using the lsi within the following electrical characteristic limits is strongly recommended for normal operation. if these electrical characteristic conditions are also exceeded, the lsi will malfunction and cause poor reliability.
hd66730/hd66731 118 dc characteristics (v cc = 2.4 v to 5.5 v, t a = ?0 to +75 c* 3 ) item symbol min typ max unit test condition notes input high voltage (1) (except osc1) vih1 0.7v cc ? cc v 5, 6 input low voltage (1) vil1 ?.3 0.2v cc vv cc = 2.4 to 3.0v 5, 6 (except osc1) ?.3 0.6 v v cc = 3.0 to 4.5v input high voltage (2) (osc1) vih2 0.7v cc ? cc v15 input low voltage (2) (osc1) vil2 0.2v cc v15 output high voltage (1) (d0?7) voh1 0.75v cc v i oh = 0.1 ma 7 output low voltage (1) (d0?7) vol1 0.2v cc vi ol = 0.1 ma 7 output high voltage (2) (except d0?7) voh2 0.8v cc v i oh = 0.04 ma 8 output low voltage (2) (except d0?7) vol2 0.2v cc vi ol = 0.04 ma 8 driver on resistance (com) r com 2 20 k w id = 0.05 ma, vlcd = 4v 13 driver on resistance (seg) r seg 2 30 k w id = 0.05 ma, vlcd = 4v 13 i/o leakage current i li ? 1 m a vin = 0 to v cc 9 pull-up mos current (reset* pin) ? p 5 50 120 m av cc = 3v vin = 0v power supply current i cc1 150 300 m ar f oscillation, external clock v cc = 3v, f osc = 215 khz 10, 14 i cc2 ?5 m a sleep mode v cc = 3v f osc = 215 khz lcd voltage vlcd 3.0 15.0 v v cc ?5 16
hd66730/hd66731 119 booster characteristics item symbol min typ max unit test condition notes* output voltage (v5out2 pin) vup2 8.2 8.9 v v cc = vci = 4.5v, i o = 0.25 ma, c = 1 m f, f osc = 215 khz, t a = 25 c 18 output voltage (v5out3 pin) vup3 7.2 7.8 v v cc = vci = 2.7v, i o = 0.25 ma, c = 1 m f, f osc = 215 khz, t a = 25 c 18 input voltage vci 1.0 5.0 v vci v cc 18, 19 ac characteristics (v cc = 2.4v to 5.5v, t a = ?0 to +75 c* 3 ) clock characteristics (v cc = 2.7 v to 5.5 v, t a = ?0 to +75 c* 3 ) item symbol min typ max unit test condition notes* external external clock frequency f cp 80 215 350 khz v cc = 2.4 to 2.7v 11 clock 80 215 550 khz v cc = 2.7 to 5.5v operation external clock duty duty 45 50 55 % external clock rise time t rcp 0.2 m s external clock fall time t rcp 0.2 m s r f oscillation clock oscillation frequency (hd66730) f osc 110 150 200 khz r f = 150 k w , v cc = 3v 12 clock oscillation frequency (hd66731) f osc 150 215 275 khz r f = 91 k w , v cc = 3v 12
hd66730/hd66731 120 system interface timing characteristics (1) (v cc = 2.4v to 4.5v, t a = ?0 to +75 c* 3 ) bus write operation item symbol min typ max unit test condition enable cycle time t cyce 500 ns figure 50 enable pulse width (high level) pw eh 250 v cc = 2.4 to 3.0v 150 v cc = 3.0 to 4.5v enable rise/fall time t er , t ef 20 figure 50 address set-up time (rs, r/ w to e) t as 80 address hold time t ah 20 data set-up time t dsw 140 data hold time t h 30 bus read operation item symbol min typ max unit test condition enable cycle time t cyce 1000 ns figure 51 enable pulse width (high level) pw eh 450 enable rise/fall time t er , t ef 25 address set-up time (rs, r/ w to e) t as 60 address hold time t ah 20 data delay time t ddr 360 data hold time t dhr 5 serial interface operation item symbol min typ max unit test condition serial clock cycle time t scyc 120 m s figure 52 serial clock (high level width) t sch 400 ns serial clock (low level width) t scl 400 serial clock rise/fall time t scr , t scf 50 chip select set-up time t csu 60 chip select hold time t ch 200 serial input data set-up time t sisu 200 serial input data hold time t sih 200 serial output data delay time t sod 360 serial output data hold time t soh 5
hd66730/hd66731 121 system interface timing characteristics (2) (v cc = 4.5v to 5.5v, t a = ?0 to +75 c* 3 ) bus write operation item symbol min typ max unit test condition enable cycle time t cyce 500 ns figure 50 enable pulse width (high level) pw eh 150 enable rise/fall time t er , t ef 20 address set-up time (rs, r/ w to e) t as 40 address hold time t ah 30 data set-up time t dsw 80 data hold time t h 30 bus read operation item symbol min typ max unit test condition enable cycle time t cyce 500 ns figure 51 enable pulse width (high level) pw eh 230 enable rise/fall time t er , t ef 20 address set-up time (rs, r/ w to e) t as 40 address hold time t ah 30 data delay time t ddr 160 data hold time t dhr 5 serial interface sequence item symbol min typ max unit test condition serial clock cycle time t scyc 0.5 20 m s figure 52 serial clock (high level width) t sch 200 ns serial clock (low level width) t scl 200 serial clock rise/fall time t scr , t scf 50 chip select set-up time t csu 60 chip select hold time t ch 100 serial input data set-up time t sisu 100 serial input data hold time t sih 100 serial output data delay time t sod 160 serial output data hold time t soh 5
hd66730/hd66731 122 hd66730 segment extension signal timing characteristics (v cc = 2.4v to 5.5v, t a = ?0 to +75 c* 3 ) item symbol min typ max unit test condition clock pulse width high level t cwh 800 ns figure 53 low level t cwl 800 clock set-up time t csu 500 data set-up time t su 300 data hold time t dh 300 m delay time t dm ?000 1000 comd set-up time t dsu 300 clock rise/fall time comd t ct1 700 pins except comd t ct2 200 reset timing characteristics (v cc = 2.4v to 5.5v, t a = ?0 to +75 c* 3 ) item symbol min typ max unit test condition reset low-level width t res 10 ms figure 54
hd66730/hd66731 123 electrical characteristics notes 1. all voltage values are referred to gnd = 0v. if the lsi is used above the absolute maximum ratings, it may become permanently damaged. using the lsi within the electrical characteristic is strongly recommended to ensure normal operation. if these electrical characteristic are exceeded, the lsi may malfunction or exhibit poor reliability. 2. v cc 3 v5 must be maintained. when the com25/comd pin is used as a extention driver interface signal (comd), gnd 3 v5 must be maintained. 3. for die products, specified at 75 c. 4. for die products, specified by the die shipment specification. 5. the following four circuits are i/o pin configurations except for liquid crystal display output. v cc pmos nmos v cc v cc pmos nmos (pull-up mos) pmos v cc pmos nmos v cc nmos nmos v cc pmos nmos (output circuit: tristate) output enable data (pull-up mos) i/o pin pins: db0/sod to db7 input pin pin: e/sclk, rs/cs * , rw/sid, im, input pin pins: reset * output pin pins: cl1, cl2, m, segd (hd66730) testd (hd66731) v cc (input circuit) pmos pmos input enable 6. applies to input pins and i/o pins, excluding the osc1 pin. 7. applies to i/o pins. 8. applies to output pins of hd66730. 9. current flowing through pull-up moss, excluding output drive moss.
hd66730/hd66731 124 10. input/output current is excluded. when input is at an intermediate level with cmos, the excessive current flows through the input circuit to the power supply. to avoid this from happening, the input level must be fixed high or low. 11. applies only to external clock operation. oscillator osc1 osc2 0.7 v 0.5 v 0.3 v cc cc cc th tl t rcp t fcp duty = 100% th th + tl open 12. applies only to the internal oscillator operation using oscillation resistor r f . osc1 osc2 r f since oscillation frequency varies depending on osc1 and osc2 terminal capacitance,wiring length to these pins should be minimized. r f : 150k ? 2% (when v cc = 3v to 4v) r f : 180k ? 2% (when v cc = 4v to 5v) recommended registor value 200 150 100 50 0 100 200 400 r f (k ) f osc (khz) 150 300 500 600 700 800 v cc = 5v (typ.) v cc = 3v (typ.)
hd66730/hd66731 125 13. rcom is the resistance between the power supply pins (v cc , v1, v4, v5) and each common signal pin (com0 to com25/com53). rseg is the resistance between the power supply pins (v cc , v2, v3, v5) and each segment signal pin (seg1 to seg71/seg119). 14. the following graphs show the relationship between operation frequency and current consumption (referential data). 0 100 200 300 400 500 0 100 200 300 400 500 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 i cc (ma) f osc or f cp (khz) v cc = 5v 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 i cc (ma) f osc or f cp (khz) v cc = 3v typ.(sleep mode) typ.(normal display) typ.(normal display) typ.(sleep mode) 15. applies to the osc1 pin. 16. each com and seg output voltage is within 0.15v of the lcd voltage (v cc , v1, v2, v3, v4, v5) when there is no load. 17. the test pin must be fixed to ground, and the im pin must also be connected to v cc or ground. 18. booster characteristics test circuits are shown below. gnd v cc 1 m f 1 m f vci c1 c2 v5out2 v5out3 + (triple boosting) + 1 m f + gnd v cc 1 m f vci c1 c2 v5out2 v5out3 (double boosting) + 1 m f + rload rload i o i o
hd66730/hd66731 126 test condition : vci=v cc =4.5v, r f =180k i o =0.1ma (ii) vup2, vup3 vs ta test condition : vci=v cc =2.7v, r f =150k i o =0.1ma ta ( c) c ( f) c ( f) vup2(v) 100 60 20 0 -20 -60 7.5 8.0 8.5 9.0 9.5 typ. ta ( c) vup3(v) 100 60 20 0 -20 -60 6.5 7.0 7.5 8.0 8.5 typ. (iii) vup2, vup3 vs capacitance test condition : vci=v cc =4.5v,r f =180k i o =0.1ma test condition : vci=v cc =2.7v, r f =150k i o =0.1ma test condition : vci=v cc =4.5v,r f =180k ta=25 c test condition : vci=v cc =2.7v, r f =150k ta=25 c 1.5 1.0 0.5 6.0 6.5 7.0 7.5 8.0 typ. vup3(v) vup2(v) 1.5 1.0 0.5 7.0 7.5 8.0 8.5 9.0 typ. boosting twice boosting three times boosting twice boosting three times (iv) vup2, vup3 vs i o boosting twice boosting three times i o (ma) vup2(v) 2.0 1.5 1.0 0.5 0.0 6.0 6.5 7.0 7.5 8.0 8.5 9.0 typ. i o (ma) vup3(v) 2.0 1.5 1.0 0.5 0.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 typ. test condition : vci=v cc , f cp =140khz, ta=25 c test condition : vci=v cc , f cp =140khz, ta=25 c vup2=v cc ?5out2 vup3=v cc ?5out3 (i) vup2,vup3 vs vci boosting twice boosting three times 5.0 4.0 3.0 2.0 4 5 6 7 8 9 10 11 vci (v) vup2(v) typ. 5.0 4.0 3.0 2.0 6 7 8 9 10 11 12 13 14 15 typ. vup3(v) vci (v) 19. vci v cc must be maintained.
hd66730/hd66731 127 load circuits ac characteristics test load circuits data bus: db0 to db7, sod test point 50 pf segment extension signals: 30 pf test point cl1, cl2, segd, m, comd
hd66730/hd66731 128 timing characteristics rs r/w e db0 to db7 vih1 vil1 vih1 vil1 t as t ah vil1 vil1 t ah pw eh t ef vih1 vil1 vih1 vil1 t er t dsw h t vih1 vil1 vih1 vil1 t cyce vil1 valid data figure 50 bus write operation rs r/w e db0 to db7 vih1 vil1 vih1 vil1 t as t ah vih1 vih1 t ah pw eh t ef vih1 vih1 t ddr dhr t t er vil1 voh1 vol1 voh1 vol1 valid data t cyce vil1 vil1 figure 51 bus read operation
hd66730/hd66731 129 cs * sclk sid sod t scyc t csu t sch t scr t scf t scl t ch t sih t sisu t soh t sod vil1 vil1 vih1 vil1 vil1 vih1 vil1 vil1 vih1 vih1 vil1 vih1 vil1 voh1 vol1 voh1 vol1 figure 52 serial interface timing cl1 cl2 segd m comd voh2 voh2 vol2 t ct t cwh t cwh voh2 t csu t cwl t ct t dh t su vol2 t dm voh2 vol2 vol2 t dsu voh2 figure 53 interface timing with extension driver
hd66730/hd66731 130 reset * vil1 vil1 t res figure 54 reset timing v cc 2.7v/4.5v * 2 0.2v t rcc 0.2v 0.2v 0.1 ms t rcc 10 ms t off * 1 t off 3 1 ms notes: 1. 2. t off compensates for the power oscillation period caused by momentary power supply oscillations. specified at 4.5v for 5-volt operation, and at 2.7v for 3-volt operation. figure 55 power supply sequence

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